Use of inner coverage information by a conservative rasterization pipeline to enable EarlyZ for conservative rasterization

ABSTRACT

Embodiments described herein are generally directed to conservative rasterization pipeline configurations that allow EarlyZ to be enabled for conservative rasterization. An embodiment of a method includes receiving, by a conservative rasterizer, a primitive; creating, by the conservative rasterizer, a pixel location stream based on the primitive and inner coverage data for each pixel within the pixel location stream indicative of whether the corresponding pixel is fully covered or partially covered by the primitive; for each block of pixels of the pixel location stream, launching, by the conservative rasterizer, a thread of a pixel shader, including causing EarlyZ to be performed or not for fully covered pixels and partially covered pixels, respectively; and generating, by the pixel shader, a stream of pixel updates by conditionally processing the pixel location stream to incorporate pixel shading characteristics, including for partially covered pixels computing a depth value and causing LateZ to be performed.

TECHNICAL FIELD

Embodiments described herein generally relate to the field of graphicsprocessing units (GPUs) and, more particularly, to various conservativerasterization pipeline configurations and methods that allow EarlyZ tobe enabled for conservative rasterization by exposing inner coverageinformation to various components of the conservative rasterizationpipeline.

BACKGROUND

It is a waste of GPU processing power to shade a pixel and then throw itout because the pixel is behind another object, particularly if thepixel shader does not change the Z value of the pixel at issue. As such,GPUs may perform an early depth test referred to as “EarlyZoptimization,” “EarlyZ rejection” or simply “EarlyZ” to identifyoccluded pixels that need not be run through the pixel shader.

Conservative rasterization supported by modern GPUs produces fragmentsfor every pixel touched by a primitive even if no sample location iscovered. FIG. 14A illustrates the results of performing a solid fill ofa primitive 1410 with conservative rasterization disabled. Regardless ofthe state of conservative rasterization, pixels (e.g., pixel 1411) thatare entirely encompassed within the primitive are filled. Whenconservative rasterization is disabled, the pixels (referred to hereinas partially covered pixels) on an edge (e.g., pixel 1412) of theprimitive 1410 are filled when the center of the pixel is encompassedwithin the primitive; otherwise they are not filled.

FIG. 14B illustrates the results of performing a solid fill of theprimitive 1410 with conservative rasterization enabled. As noted above,regardless of the state of conservative rasterization, pixels (e.g.,pixel 1413) that are entirely encompassed within the primitive arefilled. When conservative rasterization is enabled, the partiallycovered pixels (e.g., pixel 1414) on an edge of the primitive 1410 arefilled when the primitive touches the pixel regardless of how much ofthe pixel is encompassed within the primitive; otherwise they are notfilled.

Conservative rasterization is useful in several algorithms to generatebetter quality images and shadows; however, some early depth cullingGPUs cannot properly support generation of extrapolated depth values forthe fragments residing outside of the primitive. Meanwhile, even if theGPU at issue supports depth extrapolation, the use of EarlyZ isproblematic as the Z test and Z-write using the extrapolated depth valuecan be erroneous because it can extend beyond the original primitiveZ-range. As such, at present, applications typically disable EarlyZ whenmaking use of conservative rasterization.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments described here are illustrated by way of example, and not byway of limitation, in the figures of the accompanying drawings in whichlike reference numerals refer to similar elements.

FIG. 1 is a block diagram of a processing system, according to anembodiment.

FIGS. 2A-2D illustrate computing systems and graphics processors,according to some embodiments.

FIGS. 3A-3C illustrate block diagrams of additional graphics processorand compute accelerator architectures, according to some embodiments.

FIG. 4 is a block diagram of a graphics processing engine of a graphicsprocessor, according to some embodiments.

FIGS. 5A-5B illustrate thread execution logic including an array ofprocessing elements employed in a graphics processor core, according tosome embodiments.

FIG. 6 illustrates an additional execution unit, according to anembodiment.

FIG. 7 is a block diagram illustrating graphics processor instructionformats, according to some embodiments.

FIG. 8 is a block diagram of another embodiment of a graphics processor.

FIG. 9A is a block diagram illustrating a graphics processor commandformat, according to some embodiments.

FIG. 9B is a block diagram illustrating a graphics processor commandsequence, according to an embodiment.

FIG. 10 illustrates an exemplary graphics software architecture for adata processing system, according to some embodiments.

FIG. 11A is a block diagram illustrating an IP core development systemthat may be used to manufacture an integrated circuit to performoperations, according to an embodiment.

FIG. 11B illustrates a cross-section side view of an integrated circuitpackage assembly, according to some embodiments.

FIG. 11C illustrates a package assembly that includes multiple units ofhardware logic chiplets connected to a substrate, according to anembodiment.

FIG. 11D illustrates a package assembly including interchangeablechiplets, according to an embodiment.

FIG. 12 is a block diagram illustrating an exemplary system on a chipintegrated circuit that may be fabricated using one or more IP cores,according to an embodiment.

FIGS. 13A-13B are block diagrams illustrating exemplary graphicsprocessors for use within an SoC, according to some embodiments.

FIG. 14A illustrates the results of performing a solid fill of aprimitive with conservative rasterization disabled.

FIG. 14B illustrates the results of performing a solid fill of theprimitive with conservative rasterization enabled.

FIG. 15 is a block diagram illustrating a high-level architectural viewof distribution of graphics pipeline functionality between a centralprocessing unit (CPU) and a graphics processing unit (GPU) according toan embodiment.

FIG. 16 is a block diagram illustrating interactions among components ofa conservative rasterization pipeline according to a first embodiment.

FIG. 17 is a flow diagram illustrating conservative rasterizationpipeline processing according to the first embodiment.

FIG. 18 is a block diagram illustrating interactions among components ofa conservative rasterization pipeline according to a second embodiment.

FIG. 19 is a flow diagram illustrating conservative rasterizationpipeline processing according to the second embodiment.

FIG. 20 is a block diagram illustrating interactions among components ofa conservative rasterization pipeline according to a third embodiment.

DETAILED DESCRIPTION

Embodiments described herein are generally directed to conservativerasterization pipeline configurations that allow EarlyZ to be enabledfor conservative rasterization by exposing inner coverage information toone or more components of a conservative rasterization pipeline. In thismanner, the benefits of conservative rasterization can be achieved whilealso taking advantage of the performance enhancements provided byEarlyZ.

As noted above, an existing solution to address the conflicts betweenEarlyZ and conservative rasterization involves disabling EarlyZ and fromthe pixel shader outputting depth, which is clamped to the minimum andmaximum values of depth values of the primitive at issue whenconservative rasterization is enabled. Notably, however, disablingEarlyZ can have a significant impact on performance, thereby limitingthe usage of conservative rasterization. As such, embodiments describedherein seek to allow use of conservative rasterization without requiringEarlyZ to be disabled. Three different approaches are described hereinin which inner coverage information generated by a conservativerasterizer is exposed to one or more components of the conservativerasterization pipeline (e.g., the EarlyZ unit and/or the pixel shaders)so as to facilitate performance of EarlyZ even when conservativerasterization is being employed. The three different approaches arebriefly summarized immediately below and a more detailed explanation isprovided with reference to FIGS. 16-20.

According to a first embodiment, which is described in further detailwith reference to FIGS. 16-17, EarlyZ is enabled for fully coveredpixels as though conservative rasterization is off and for partiallycovered pixels EarlyZ is disabled or becomes a pass through. Based oninner coverage data (e.g., an inner coverage mask) generated by theconservative rasterizer and exposed to the pixel shaders, the pixelshaders may compute the output depth value only for partially coveredpixels and a late depth test, referred to as “LateZ optimization,”“LateZ rejection” or simply “LateZ” to identify occluded pixels thatneed not be run through graphics pipeline stages subsequent to pixelshading, is performed with reference to this output depth value producedby the pixel shaders. In this embodiment, inner coverage data for eachblock of pixels processed after the conservative rasterizer may betracked at a per-pixel level to facilitate downstream processing asdescribed further below.

According to a second embodiment, which is described in further detailwith reference to FIGS. 18-19, the conservative rasterizer launchespixel shader threads for fully covered pixels as though conservativerasterization is off with EarlyZ enabled. At the same time, theconservative rasterizer may accumulate partially covered pixels in abuffer and launches them separately with EarlyZ disabled. For partiallycovered pixels, the pixel shader may compute depth values and the LateZtest follows as in the first embodiment. This approach may be suitablefor GPU architectures that are limited to performing EarlyZ at the levelof granularity of a block of pixels and are not capable of performingEarlyZ for a subset of pixels in a particular block. In this embodiment,inner coverage data for each block of pixels processed after theconservative rasterizer may be tracked at the pixel block level ofgranularity instead of on a per-pixel basis to facilitate downstreamprocessing as described further below. In this manner, conditionalprocessing on a pixel-by-pixel basis within the pixel shader can beavoided as the partially and fully covered pixels are processedseparately via different pixel shader threads.

Finally, according to a third embodiment, which is described in furtherdetail with reference to FIG. 20, the EarlyZ unit conditionallyprocesses pixels based on the inner coverage data by clamping theextrapolated depth value for partially covered pixels to the minimum andthe maximum values for the primitive being rasterized so as to allowEarlyZ to be enabled for both partially and fully covered pixels.

System Overview

FIG. 1 is a block diagram of a processing system 100, according to anembodiment. System 100 may be used in a single processor desktop system,a multiprocessor workstation system, or a server system having a largenumber of processors 102 or processor cores 107. In one embodiment, thesystem 100 is a processing platform incorporated within asystem-on-a-chip (SoC) integrated circuit for use in mobile, handheld,or embedded devices such as within Internet-of-things (IoT) devices withwired or wireless connectivity to a local or wide area network.

In one embodiment, system 100 can include, couple with, or be integratedwithin: a server-based gaming platform; a game console, including a gameand media console; a mobile gaming console, a handheld game console, oran online game console. In some embodiments the system 100 is part of amobile phone, smart phone, tablet computing device or mobileInternet-connected device such as a laptop with low internal storagecapacity. Processing system 100 can also include, couple with, or beintegrated within: a wearable device, such as a smart watch wearabledevice; smart eyewear or clothing enhanced with augmented reality (AR)or virtual reality (VR) features to provide visual, audio or tactileoutputs to supplement real world visual, audio or tactile experiences orotherwise provide text, audio, graphics, video, holographic images orvideo, or tactile feedback; other augmented reality (AR) device; orother virtual reality (VR) device. In some embodiments, the processingsystem 100 includes or is part of a television or set top box device. Inone embodiment, system 100 can include, couple with, or be integratedwithin a self-driving vehicle such as a bus, tractor trailer, car, motoror electric power cycle, plane or glider (or any combination thereof).The self-driving vehicle may use system 100 to process the environmentsensed around the vehicle.

In some embodiments, the one or more processors 102 each include one ormore processor cores 107 to process instructions which, when executed,perform operations for system or user software. In some embodiments, atleast one of the one or more processor cores 107 is configured toprocess a specific instruction set 109. In some embodiments, instructionset 109 may facilitate Complex Instruction Set Computing (CISC), ReducedInstruction Set Computing (RISC), or computing via a Very LongInstruction Word (VLIW). One or more processor cores 107 may process adifferent instruction set 109, which may include instructions tofacilitate the emulation of other instruction sets. Processor core 107may also include other processing devices, such as a Digital SignalProcessor (DSP).

In some embodiments, the processor 102 includes cache memory 104.Depending on the architecture, the processor 102 can have a singleinternal cache or multiple levels of internal cache. In someembodiments, the cache memory is shared among various components of theprocessor 102. In some embodiments, the processor 102 also uses anexternal cache (e.g., a Level-3 (L3) cache or Last Level Cache (LLC))(not shown), which may be shared among processor cores 107 using knowncache coherency techniques. A register file 106 can be additionallyincluded in processor 102 and may include different types of registersfor storing different types of data (e.g., integer registers, floatingpoint registers, status registers, and an instruction pointer register).Some registers may be general-purpose registers, while other registersmay be specific to the design of the processor 102.

In some embodiments, one or more processor(s) 102 are coupled with oneor more interface bus(es) 110 to transmit communication signals such asaddress, data, or control signals between processor 102 and othercomponents in the system 100. The interface bus 110, in one embodiment,can be a processor bus, such as a version of the Direct Media Interface(DMI) bus. However, processor busses are not limited to the DMI bus, andmay include one or more Peripheral Component Interconnect buses (e.g.,PCI, PCI express), memory busses, or other types of interface busses. Inone embodiment the processor(s) 102 include an integrated memorycontroller 116 and a platform controller hub 130. The memory controller116 facilitates communication between a memory device and othercomponents of the system 100, while the platform controller hub (PCH)130 provides connections to I/O devices via a local I/O bus.

The memory device 120 can be a dynamic random-access memory (DRAM)device, a static random-access memory (SRAM) device, flash memorydevice, phase-change memory device, or some other memory device havingsuitable performance to serve as process memory. In one embodiment thememory device 120 can operate as system memory for the system 100, tostore data 122 and instructions 121 for use when the one or moreprocessors 102 executes an application or process. Memory controller 116also couples with an optional external graphics processor 118, which maycommunicate with the one or more graphics processors 108 in processors102 to perform graphics and media operations. In some embodiments,graphics, media, and or compute operations may be assisted by anaccelerator 112 which is a coprocessor that can be configured to performa specialized set of graphics, media, or compute operations. Forexample, in one embodiment the accelerator 112 is a matrixmultiplication accelerator used to optimize machine learning or computeoperations. In one embodiment the accelerator 112 is a ray-tracingaccelerator that can be used to perform ray-tracing operations inconcert with the graphics processor 108. In one embodiment, an externalaccelerator 119 may be used in place of or in concert with theaccelerator 112.

In some embodiments a display device 111 can connect to the processor(s)102. The display device 111 can be one or more of an internal displaydevice, as in a mobile electronic device or a laptop device or anexternal display device attached via a display interface (e.g.,DisplayPort, etc.). In one embodiment the display device 111 can be ahead mounted display (HMD) such as a stereoscopic display device for usein virtual reality (VR) applications or augmented reality (AR)applications.

In some embodiments the platform controller hub 130 enables peripheralsto connect to memory device 120 and processor 102 via a high-speed I/Obus. The I/O peripherals include, but are not limited to, an audiocontroller 146, a network controller 134, a firmware interface 128, awireless transceiver 126, touch sensors 125, a data storage device 124(e.g., non-volatile memory, volatile memory, hard disk drive, flashmemory, NAND, 3D NAND, 3D XPoint, etc.). The data storage device 124 canconnect via a storage interface (e.g., SATA) or via a peripheral bus,such as a Peripheral Component Interconnect bus (e.g., PCI, PCIexpress). The touch sensors 125 can include touch screen sensors,pressure sensors, or fingerprint sensors. The wireless transceiver 126can be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile networktransceiver such as a 3G, 4G, 5G, or Long-Term Evolution (LTE)transceiver. The firmware interface 128 enables communication withsystem firmware, and can be, for example, a unified extensible firmwareinterface (UEFI). The network controller 134 can enable a networkconnection to a wired network. In some embodiments, a high-performancenetwork controller (not shown) couples with the interface bus 110. Theaudio controller 146, in one embodiment, is a multi-channel highdefinition audio controller. In one embodiment the system 100 includesan optional legacy I/O controller 140 for coupling legacy (e.g.,Personal System 2 (PS/2)) devices to the system. The platform controllerhub 130 can also connect to one or more Universal Serial Bus (USB)controllers 142 connect input devices, such as keyboard and mouse 143combinations, a camera 144, or other USB input devices.

It will be appreciated that the system 100 shown is exemplary and notlimiting, as other types of data processing systems that are differentlyconfigured may also be used. For example, an instance of the memorycontroller 116 and platform controller hub 130 may be integrated into adiscreet external graphics processor, such as the external graphicsprocessor 118. In one embodiment the platform controller hub 130 and/ormemory controller 116 may be external to the one or more processor(s)102. For example, the system 100 can include an external memorycontroller 116 and platform controller hub 130, which may be configuredas a memory controller hub and peripheral controller hub within a systemchipset that is in communication with the processor(s) 102.

For example, circuit boards (“sleds”) can be used on which componentssuch as CPUs, memory, and other components are placed are designed forincreased thermal performance. In some examples, processing componentssuch as the processors are located on a top side of a sled while nearmemory, such as DIMMs, are located on a bottom side of the sled. As aresult of the enhanced airflow provided by this design, the componentsmay operate at higher frequencies and power levels than in typicalsystems, thereby increasing performance. Furthermore, the sleds areconfigured to blindly mate with power and data communication cables in arack, thereby enhancing their ability to be quickly removed, upgraded,reinstalled, and/or replaced. Similarly, individual components locatedon the sleds, such as processors, accelerators, memory, and data storagedrives, are configured to be easily upgraded due to their increasedspacing from each other. In the illustrative embodiment, the componentsadditionally include hardware attestation features to prove theirauthenticity.

A data center can utilize a single network architecture (“fabric”) thatsupports multiple other network architectures including Ethernet andOmni-Path. The sleds can be coupled to switches via optical fibers,which provide higher bandwidth and lower latency than typical twistedpair cabling (e.g., Category 5, Category 5e, Category 6, etc.). Due tothe high bandwidth, low latency interconnections and networkarchitecture, the data center may, in use, pool resources, such asmemory, accelerators (e.g., GPUs, graphics accelerators, FPGAs, ASICs,neural network and/or artificial intelligence accelerators, etc.), anddata storage drives that are physically disaggregated, and provide themto compute resources (e.g., processors) on an as needed basis, enablingthe compute resources to access the pooled resources as if they werelocal.

A power supply or source can provide voltage and/or current to system100 or any component or system described herein. In one example, thepower supply includes an AC to DC (alternating current to directcurrent) adapter to plug into a wall outlet. Such AC power can berenewable energy (e.g., solar power) power source. In one example, powersource includes a DC power source, such as an external AC to DCconverter. In one example, power source or power supply includeswireless charging hardware to charge via proximity to a charging field.In one example, power source can include an internal battery,alternating current supply, motion-based power supply, solar powersupply, or fuel cell source.

FIGS. 2A-2D illustrate computing systems and graphics processorsprovided by embodiments described herein. The elements of FIGS. 2A-2Dhaving the same reference numbers (or names) as the elements of anyother figure herein can operate or function in any manner similar tothat described elsewhere herein, but are not limited to such.

FIG. 2A is a block diagram of an embodiment of a processor 200 havingone or more processor cores 202A-202N, an integrated memory controller214, and an integrated graphics processor 208. Processor 200 can includeadditional cores up to and including additional core 202N represented bythe dashed lined boxes. Each of processor cores 202A-202N includes oneor more internal cache units 204A-204N. In some embodiments eachprocessor core also has access to one or more shared cached units 206.The internal cache units 204A-204N and shared cache units 206 representa cache memory hierarchy within the processor 200. The cache memoryhierarchy may include at least one level of instruction and data cachewithin each processor core and one or more levels of shared mid-levelcache, such as a Level 2 (L2), Level 3 (L3), Level 4 (L4), or otherlevels of cache, where the highest level of cache before external memoryis classified as the LLC. In some embodiments, cache coherency logicmaintains coherency between the various cache units 206 and 204A-204N.

In some embodiments, processor 200 may also include a set of one or morebus controller units 216 and a system agent core 210. The one or morebus controller units 216 manage a set of peripheral buses, such as oneor more PCI or PCI express busses. System agent core 210 providesmanagement functionality for the various processor components. In someembodiments, system agent core 210 includes one or more integratedmemory controllers 214 to manage access to various external memorydevices (not shown).

In some embodiments, one or more of the processor cores 202A-202Ninclude support for simultaneous multi-threading. In such embodiment,the system agent core 210 includes components for coordinating andoperating cores 202A-202N during multi-threaded processing. System agentcore 210 may additionally include a power control unit (PCU), whichincludes logic and components to regulate the power state of processorcores 202A-202N and graphics processor 208.

In some embodiments, processor 200 additionally includes graphicsprocessor 208 to execute graphics processing operations. In someembodiments, the graphics processor 208 couples with the set of sharedcache units 206, and the system agent core 210, including the one ormore integrated memory controllers 214. In some embodiments, the systemagent core 210 also includes a display controller 211 to drive graphicsprocessor output to one or more coupled displays. In some embodiments,display controller 211 may also be a separate module coupled with thegraphics processor via at least one interconnect, or may be integratedwithin the graphics processor 208.

In some embodiments, a ring-based interconnect unit 212 is used tocouple the internal components of the processor 200. However, analternative interconnect unit may be used, such as a point-to-pointinterconnect, a switched interconnect, or other techniques, includingtechniques well known in the art. In some embodiments, graphicsprocessor 208 couples with the ring interconnect 212 via an I/O link213.

The exemplary I/O link 213 represents at least one of multiple varietiesof I/O interconnects, including an on package I/O interconnect whichfacilitates communication between various processor components and ahigh-performance embedded memory module 218, such as an eDRAM module. Insome embodiments, each of the processor cores 202A-202N and graphicsprocessor 208 can use embedded memory modules 218 as a shared Last LevelCache.

In some embodiments, processor cores 202A-202N are homogenous coresexecuting the same instruction set architecture. In another embodiment,processor cores 202A-202N are heterogeneous in terms of instruction setarchitecture (ISA), where one or more of processor cores 202A-202Nexecute a first instruction set, while at least one of the other coresexecutes a subset of the first instruction set or a differentinstruction set. In one embodiment, processor cores 202A-202N areheterogeneous in terms of microarchitecture, where one or more coreshaving a relatively higher power consumption couple with one or morepower cores having a lower power consumption. In one embodiment,processor cores 202A-202N are heterogeneous in terms of computationalcapability. Additionally, processor 200 can be implemented on one ormore chips or as an SoC integrated circuit having the illustratedcomponents, in addition to other components.

FIG. 2B is a block diagram of hardware logic of a graphics processorcore 219, according to some embodiments described herein. Elements ofFIG. 2B having the same reference numbers (or names) as the elements ofany other figure herein can operate or function in any manner similar tothat described elsewhere herein, but are not limited to such. Thegraphics processor core 219, sometimes referred to as a core slice, canbe one or multiple graphics cores within a modular graphics processor.The graphics processor core 219 is exemplary of one graphics core slice,and a graphics processor as described herein may include multiplegraphics core slices based on target power and performance envelopes.Each graphics processor core 219 can include a fixed function block 230coupled with multiple sub-cores 221A-221F, also referred to assub-slices, that include modular blocks of general-purpose and fixedfunction logic.

In some embodiments, the fixed function block 230 includes ageometry/fixed function pipeline 231 that can be shared by all sub-coresin the graphics processor core 219, for example, in lower performanceand/or lower power graphics processor implementations. In variousembodiments, the geometry/fixed function pipeline 231 includes a 3Dfixed function pipeline (e.g., 3D pipeline 312 as in FIG. 3 and FIG. 4,described below) a video front-end unit, a thread spawner and threaddispatcher, and a unified return buffer manager, which manages unifiedreturn buffers (e.g., unified return buffer 418 in FIG. 4, as describedbelow).

In one embodiment the fixed function block 230 also includes a graphicsSoC interface 232, a graphics microcontroller 233, and a media pipeline234. The graphics SoC interface 232 provides an interface between thegraphics processor core 219 and other processor cores within a system ona chip integrated circuit. The graphics microcontroller 233 is aprogrammable sub-processor that is configurable to manage variousfunctions of the graphics processor core 219, including thread dispatch,scheduling, and pre-emption. The media pipeline 234 (e.g., mediapipeline 316 of FIG. 3 and FIG. 4) includes logic to facilitate thedecoding, encoding, pre-processing, and/or post-processing of multimediadata, including image and video data. The media pipeline 234 implementmedia operations via requests to compute or sampling logic within thesub-cores 221-221F.

In one embodiment the SoC interface 232 enables the graphics processorcore 219 to communicate with general-purpose application processor cores(e.g., CPUs) and/or other components within an SoC, including memoryhierarchy elements such as a shared last level cache memory, the systemRAM, and/or embedded on-chip or on-package DRAM. The SoC interface 232can also enable communication with fixed function devices within theSoC, such as camera imaging pipelines, and enables the use of and/orimplements global memory atomics that may be shared between the graphicsprocessor core 219 and CPUs within the SoC. The SoC interface 232 canalso implement power management controls for the graphics processor core219 and enable an interface between a clock domain of the graphic core219 and other clock domains within the SoC. In one embodiment the SoCinterface 232 enables receipt of command buffers from a command streamerand global thread dispatcher that are configured to provide commands andinstructions to each of one or more graphics cores within a graphicsprocessor. The commands and instructions can be dispatched to the mediapipeline 234, when media operations are to be performed, or a geometryand fixed function pipeline (e.g., geometry and fixed function pipeline231, geometry and fixed function pipeline 237) when graphics processingoperations are to be performed.

The graphics microcontroller 233 can be configured to perform variousscheduling and management tasks for the graphics processor core 219. Inone embodiment the graphics microcontroller 233 can perform graphicsand/or compute workload scheduling on the various graphics parallelengines within execution unit (EU) arrays 222A-222F, 224A-224F withinthe sub-cores 221A-221F. In this scheduling model, host softwareexecuting on a CPU core of an SoC including the graphics processor core219 can submit workloads one of multiple graphic processor doorbells,which invokes a scheduling operation on the appropriate graphics engine.Scheduling operations include determining which workload to run next,submitting a workload to a command streamer, pre-empting existingworkloads running on an engine, monitoring progress of a workload, andnotifying host software when a workload is complete. In one embodimentthe graphics microcontroller 233 can also facilitate low-power or idlestates for the graphics processor core 219, providing the graphicsprocessor core 219 with the ability to save and restore registers withinthe graphics processor core 219 across low-power state transitionsindependently from the operating system and/or graphics driver softwareon the system.

The graphics processor core 219 may have greater than or fewer than theillustrated sub-cores 221A-221F, up to N modular sub-cores. For each setof N sub-cores, the graphics processor core 219 can also include sharedfunction logic 235, shared and/or cache memory 236, a geometry/fixedfunction pipeline 237, as well as additional fixed function logic 238 toaccelerate various graphics and compute processing operations. Theshared function logic 235 can include logic units associated with theshared function logic 420 of FIG. 4 (e.g., sampler, math, and/orinter-thread communication logic) that can be shared by each N sub-coreswithin the graphics processor core 219. The shared and/or cache memory236 can be a last-level cache for the set of N sub-cores 221A-221Fwithin the graphics processor core 219, and can also serve as sharedmemory that is accessible by multiple sub-cores. The geometry/fixedfunction pipeline 237 can be included instead of the geometry/fixedfunction pipeline 231 within the fixed function block 230 and caninclude the same or similar logic units.

In one embodiment the graphics processor core 219 includes additionalfixed function logic 238 that can include various fixed functionacceleration logic for use by the graphics processor core 219. In oneembodiment the additional fixed function logic 238 includes anadditional geometry pipeline for use in position only shading. Inposition-only shading, two geometry pipelines exist, the full geometrypipeline within the geometry/fixed function pipeline 238, 231, and acull pipeline, which is an additional geometry pipeline which may beincluded within the additional fixed function logic 238. In oneembodiment the cull pipeline is a trimmed down version of the fullgeometry pipeline. The full pipeline and the cull pipeline can executedifferent instances of the same application, each instance having aseparate context. Position only shading can hide long cull runs ofdiscarded triangles, enabling shading to be completed earlier in someinstances. For example and in one embodiment the cull pipeline logicwithin the additional fixed function logic 238 can execute positionshaders in parallel with the main application and generally generatescritical results faster than the full pipeline, as the cull pipelinefetches and shades only the position attribute of the vertices, withoutperforming rasterization and rendering of the pixels to the framebuffer. The cull pipeline can use the generated critical results tocompute visibility information for all the triangles without regard towhether those triangles are culled. The full pipeline (which in thisinstance may be referred to as a replay pipeline) can consume thevisibility information to skip the culled triangles to shade only thevisible triangles that are finally passed to the rasterization phase.

In one embodiment the additional fixed function logic 238 can alsoinclude machine-learning acceleration logic, such as fixed functionmatrix multiplication logic, for implementations including optimizationsfor machine learning training or inferencing.

Within each graphics sub-core 221A-221F includes a set of executionresources that may be used to perform graphics, media, and computeoperations in response to requests by graphics pipeline, media pipeline,or shader programs. The graphics sub-cores 221A-221F include multiple EUarrays 222A-222F, 224A-224F, thread dispatch and inter-threadcommunication (TD/IC) logic 223A-223F, a 3D (e.g., texture) sampler225A-225F, a media sampler 206A-206F, a shader processor 227A-227F, andshared local memory (SLM) 228A-228F. The EU arrays 222A-222F, 224A-224Feach include multiple execution units, which are general-purposegraphics processing units capable of performing floating-point andinteger/fixed-point logic operations in service of a graphics, media, orcompute operation, including graphics, media, or compute shaderprograms. The TD/IC logic 223A-223F performs local thread dispatch andthread control operations for the execution units within a sub-core andfacilitate communication between threads executing on the executionunits of the sub-core. The 3D sampler 225A-225F can read texture orother 3D graphics related data into memory. The 3D sampler can readtexture data differently based on a configured sample state and thetexture format associated with a given texture. The media sampler206A-206F can perform similar read operations based on the type andformat associated with media data. In one embodiment, each graphicssub-core 221A-221F can alternately include a unified 3D and mediasampler. Threads executing on the execution units within each of thesub-cores 221A-221F can make use of shared local memory 228A-228F withineach sub-core, to enable threads executing within a thread group toexecute using a common pool of on-chip memory.

FIG. 2C illustrates a graphics processing unit (GPU) 239 that includesdedicated sets of graphics processing resources arranged into multi-coregroups 240A-240N. While the details of only a single multi-core group240A are provided, it will be appreciated that the other multi-coregroups 240B-240N may be equipped with the same or similar sets ofgraphics processing resources.

As illustrated, a multi-core group 240A may include a set of graphicscores 243, a set of tensor cores 244, and a set of ray tracing cores245. A scheduler/dispatcher 241 schedules and dispatches the graphicsthreads for execution on the various cores 243, 244, 245. A set ofregister files 242 store operand values used by the cores 243, 244, 245when executing the graphics threads. These may include, for example,integer registers for storing integer values, floating point registersfor storing floating point values, vector registers for storing packeddata elements (integer and/or floating point data elements) and tileregisters for storing tensor/matrix values. In one embodiment, the tileregisters are implemented as combined sets of vector registers.

One or more combined level 1 (L1) caches and shared memory units 247store graphics data such as texture data, vertex data, pixel data, raydata, bounding volume data, etc., locally within each multi-core group240A. One or more texture units 247 can also be used to performtexturing operations, such as texture mapping and sampling. A Level 2(L2) cache 253 shared by all or a subset of the multi-core groups240A-240N stores graphics data and/or instructions for multipleconcurrent graphics threads. As illustrated, the L2 cache 253 may beshared across a plurality of multi-core groups 240A-240N. One or morememory controllers 248 couple the GPU 239 to a memory 249 which may be asystem memory (e.g., DRAM) and/or a dedicated graphics memory (e.g.,GDDR6 memory).

Input/output (I/O) circuitry 250 couples the GPU 239 to one or more I/Odevices 252 such as digital signal processors (DSPs), networkcontrollers, or user input devices. An on-chip interconnect may be usedto couple the I/O devices 252 to the GPU 239 and memory 249. One or moreI/O memory management units (IOMMUs) 251 of the I/O circuitry 250 couplethe I/O devices 252 directly to the system memory 249. In oneembodiment, the IOMMU 251 manages multiple sets of page tables to mapvirtual addresses to physical addresses in system memory 249. In thisembodiment, the I/O devices 252, CPU(s) 246, and GPU(s) 239 may sharethe same virtual address space.

In one implementation, the IOMMU 251 supports virtualization. In thiscase, it may manage a first set of page tables to map guest/graphicsvirtual addresses to guest/graphics physical addresses and a second setof page tables to map the guest/graphics physical addresses tosystem/host physical addresses (e.g., within system memory 249). Thebase addresses of each of the first and second sets of page tables maybe stored in control registers and swapped out on a context switch(e.g., so that the new context is provided with access to the relevantset of page tables). While not illustrated in FIG. 2C, each of the cores243, 244, 245 and/or multi-core groups 240A-240N may include translationlookaside buffers (TLBs) to cache guest virtual to guest physicaltranslations, guest physical to host physical translations, and guestvirtual to host physical translations.

In one embodiment, the CPUs 246, GPUs 239, and I/O devices 252 areintegrated on a single semiconductor chip and/or chip package. Theillustrated memory 249 may be integrated on the same chip or may becoupled to the memory controllers 248 via an off-chip interface. In oneimplementation, the memory 249 comprises GDDR6 memory which shares thesame virtual address space as other physical system-level memories,although the underlying principles are not limited to this specificimplementation.

In one embodiment, the tensor cores 244 include a plurality of executionunits specifically designed to perform matrix operations, which are thefundamental compute operation used to perform deep learning operations.For example, simultaneous matrix multiplication operations may be usedfor neural network training and inferencing. The tensor cores 244 mayperform matrix processing using a variety of operand precisionsincluding single precision floating-point (e.g., 32 bits),half-precision floating point (e.g., 16 bits), integer words (16 bits),bytes (8 bits), and half-bytes (4 bits). In one embodiment, a neuralnetwork implementation extracts features of each rendered scene,potentially combining details from multiple frames, to construct ahigh-quality final image.

In deep learning implementations, parallel matrix multiplication workmay be scheduled for execution on the tensor cores 244. The training ofneural networks, in particular, requires a significant number matrix dotproduct operations. In order to process an inner-product formulation ofan N×N×N matrix multiply, the tensor cores 244 may include at least Ndot-product processing elements. Before the matrix multiply begins, oneentire matrix is loaded into tile registers and at least one column of asecond matrix is loaded each cycle for N cycles. Each cycle, there are Ndot products that are processed.

Matrix elements may be stored at different precisions depending on theparticular implementation, including 16-bit words, 8-bit bytes (e.g.,INT8) and 4-bit half-bytes (e.g., INT4). Different precision modes maybe specified for the tensor cores 244 to ensure that the most efficientprecision is used for different workloads (e.g., such as inferencingworkloads which can tolerate quantization to bytes and half-bytes).

In one embodiment, the ray tracing cores 245 accelerate ray tracingoperations for both real-time ray tracing and non-real-time ray tracingimplementations. In particular, the ray tracing cores 245 include raytraversal/intersection circuitry for performing ray traversal usingbounding volume hierarchies (BVHs) and identifying intersections betweenrays and primitives enclosed within the BVH volumes. The ray tracingcores 245 may also include circuitry for performing depth testing andculling (e.g., using a Z buffer or similar arrangement). In oneimplementation, the ray tracing cores 245 perform traversal andintersection operations in concert with the image denoising techniquesdescribed herein, at least a portion of which may be executed on thetensor cores 244. For example, in one embodiment, the tensor cores 244implement a deep learning neural network to perform denoising of framesgenerated by the ray tracing cores 245. However, the CPU(s) 246,graphics cores 243, and/or ray tracing cores 245 may also implement allor a portion of the denoising and/or deep learning algorithms.

In addition, as described above, a distributed approach to denoising maybe employed in which the GPU 239 is in a computing device coupled toother computing devices over a network or high speed interconnect. Inthis embodiment, the interconnected computing devices share neuralnetwork learning/training data to improve the speed with which theoverall system learns to perform denoising for different types of imageframes and/or different graphics applications.

In one embodiment, the ray tracing cores 245 process all BVH traversaland ray-primitive intersections, saving the graphics cores 243 frombeing overloaded with thousands of instructions per ray. In oneembodiment, each ray tracing core 245 includes a first set ofspecialized circuitry for performing bounding box tests (e.g., fortraversal operations) and a second set of specialized circuitry forperforming the ray-triangle intersection tests (e.g., intersecting rayswhich have been traversed). Thus, in one embodiment, the multi-coregroup 240A can simply launch a ray probe, and the ray tracing cores 245independently perform ray traversal and intersection and return hit data(e.g., a hit, no hit, multiple hits, etc.) to the thread context. Theother cores 243, 244 are freed to perform other graphics or compute workwhile the ray tracing cores 245 perform the traversal and intersectionoperations.

In one embodiment, each ray tracing core 245 includes a traversal unitto perform BVH testing operations and an intersection unit whichperforms ray-primitive intersection tests. The intersection unitgenerates a “hit”, “no hit”, or “multiple hit” response, which itprovides to the appropriate thread. During the traversal andintersection operations, the execution resources of the other cores(e.g., graphics cores 243 and tensor cores 244) are freed to performother forms of graphics work.

In one particular embodiment described below, a hybrid rasterization/raytracing approach is used in which work is distributed between thegraphics cores 243 and ray tracing cores 245.

In one embodiment, the ray tracing cores 245 (and/or other cores 243,244) include hardware support for a ray tracing instruction set such asMicrosoft's DirectX Ray Tracing (DXR) which includes a DispatchRayscommand, as well as ray-generation, closest-hit, any-hit, and missshaders, which enable the assignment of unique sets of shaders andtextures for each object. Another ray tracing platform which may besupported by the ray tracing cores 245, graphics cores 243 and tensorcores 244 is Vulkan 1.1.85. Note, however, that the underlyingprinciples are not limited to any particular ray tracing ISA.

In general, the various cores 245, 244, 243 may support a ray tracinginstruction set that includes instructions/functions for ray generation,closest hit, any hit, ray-primitive intersection, per-primitive andhierarchical bounding box construction, miss, visit, and exceptions.More specifically, one embodiment includes ray tracing instructions toperform the following functions:

Ray Generation—Ray generation instructions may be executed for eachpixel, sample, or other user-defined work assignment.

Closest Hit—A closest hit instruction may be executed to locate theclosest intersection point of a ray with primitives within a scene.

Any Hit—An any hit instruction identifies multiple intersections betweena ray and primitives within a scene, potentially to identify a newclosest intersection point.

Intersection—An intersection instruction performs a ray-primitiveintersection test and outputs a result.

Per-primitive Bounding box Construction—This instruction builds abounding box around a given primitive or group of primitives (e.g., whenbuilding a new BVH or other acceleration data structure).

Miss—Indicates that a ray misses all geometry within a scene, orspecified region of a scene.

Visit—Indicates the children volumes a ray will traverse.

Exceptions—Includes various types of exception handlers (e.g., invokedfor various error conditions).

FIG. 2D is a block diagram of general purpose graphics processing unit(GPGPU) 270 that can be configured as a graphics processor and/orcompute accelerator, according to embodiments described herein. TheGPGPU 270 can interconnect with host processors (e.g., one or moreCPU(s) 246) and memory 271, 272 via one or more system and/or memorybusses. In one embodiment the memory 271 is system memory that may beshared with the one or more CPU(s) 246, while memory 272 is devicememory that is dedicated to the GPGPU 270. In one embodiment, componentswithin the GPGPU 270 and device memory 272 may be mapped into memoryaddresses that are accessible to the one or more CPU(s) 246. Access tomemory 271 and 272 may be facilitated via a memory controller 268. Inone embodiment the memory controller 268 includes an internal directmemory access (DMA) controller 269 or can include logic to performoperations that would otherwise be performed by a DMA controller.

The GPGPU 270 includes multiple cache memories, including an L2 cache253, L1 cache 254, an instruction cache 255, and shared memory 256, atleast a portion of which may also be partitioned as a cache memory. TheGPGPU 270 also includes multiple compute units 260A-260N. Each computeunit 260A-260N includes a set of vector registers 261, scalar registers262, vector logic units 263, and scalar logic units 264. The computeunits 260A-260N can also include local shared memory 265 and a programcounter 266. The compute units 260A-260N can couple with a constantcache 267, which can be used to store constant data, which is data thatwill not change during the run of kernel or shader program that executeson the GPGPU 270. In one embodiment the constant cache 267 is a scalardata cache and cached data can be fetched directly into the scalarregisters 262.

During operation, the one or more CPU(s) 246 can write commands intoregisters or memory in the GPGPU 270 that has been mapped into anaccessible address space. The command processors 257 can read thecommands from registers or memory and determine how those commands willbe processed within the GPGPU 270. A thread dispatcher 258 can then beused to dispatch threads to the compute units 260A-260N to perform thosecommands. Each compute unit 260A-260N can execute threads independentlyof the other compute units. Additionally each compute unit 260A-260N canbe independently configured for conditional computation and canconditionally output the results of computation to memory. The commandprocessors 257 can interrupt the one or more CPU(s) 246 when thesubmitted commands are complete.

FIGS. 3A-3C illustrate block diagrams of additional graphics processorand compute accelerator architectures provided by embodiments describedherein. The elements of FIGS. 3A-3C having the same reference numbers(or names) as the elements of any other figure herein can operate orfunction in any manner similar to that described elsewhere herein, butare not limited to such.

FIG. 3A is a block diagram of a graphics processor 300, which may be adiscrete graphics processing unit, or may be a graphics processorintegrated with a plurality of processing cores, or other semiconductordevices such as, but not limited to, memory devices or networkinterfaces. In some embodiments, the graphics processor communicates viaa memory mapped I/O interface to registers on the graphics processor andwith commands placed into the processor memory. In some embodiments,graphics processor 300 includes a memory interface 314 to access memory.Memory interface 314 can be an interface to local memory, one or moreinternal caches, one or more shared external caches, and/or to systemmemory.

In some embodiments, graphics processor 300 also includes a displaycontroller 302 to drive display output data to a display device 318.Display controller 302 includes hardware for one or more overlay planesfor the display and composition of multiple layers of video or userinterface elements. The display device 318 can be an internal orexternal display device. In one embodiment the display device 318 is ahead mounted display device, such as a virtual reality (VR) displaydevice or an augmented reality (AR) display device. In some embodiments,graphics processor 300 includes a video codec engine 306 to encode,decode, or transcode media to, from, or between one or more mediaencoding formats, including, but not limited to Moving Picture ExpertsGroup (MPEG) formats such as MPEG-2, Advanced Video Coding (AVC) formatssuch as H.264/MPEG-4 AVC, H.265/HEVC, Alliance for Open Media (AOMedia)VP8, VP9, as well as the Society of Motion Picture & TelevisionEngineers (SMPTE) 421M/VC-1, and Joint Photographic Experts Group (JPEG)formats such as JPEG, and Motion JPEG (MJPEG) formats.

In some embodiments, graphics processor 300 includes a block imagetransfer (BLIT) engine 304 to perform two-dimensional (2D) rasterizeroperations including, for example, bit-boundary block transfers.However, in one embodiment, 2D graphics operations are performed usingone or more components of graphics processing engine (GPE) 310. In someembodiments, GPE 310 is a compute engine for performing graphicsoperations, including three-dimensional (3D) graphics operations andmedia operations.

In some embodiments, GPE 310 includes a 3D pipeline 312 for performing3D operations, such as rendering three-dimensional images and scenesusing processing functions that act upon 3D primitive shapes (e.g.,rectangle, triangle, etc.). The 3D pipeline 312 includes programmableand fixed function elements that perform various tasks within theelement and/or spawn execution threads to a 3D/Media sub-system 315.While 3D pipeline 312 can be used to perform media operations, anembodiment of GPE 310 also includes a media pipeline 316 that isspecifically used to perform media operations, such as videopost-processing and image enhancement.

In some embodiments, media pipeline 316 includes fixed function orprogrammable logic units to perform one or more specialized mediaoperations, such as video decode acceleration, video de-interlacing, andvideo encode acceleration in place of, or on behalf of video codecengine 306. In some embodiments, media pipeline 316 additionallyincludes a thread spawning unit to spawn threads for execution on3D/Media sub-system 315. The spawned threads perform computations forthe media operations on one or more graphics execution units included in3D/Media sub-system 315.

In some embodiments, 3D/Media subsystem 315 includes logic for executingthreads spawned by 3D pipeline 312 and media pipeline 316. In oneembodiment, the pipelines send thread execution requests to 3D/Mediasubsystem 315, which includes thread dispatch logic for arbitrating anddispatching the various requests to available thread executionresources. The execution resources include an array of graphicsexecution units to process the 3D and media threads. In someembodiments, 3D/Media subsystem 315 includes one or more internal cachesfor thread instructions and data. In some embodiments, the subsystemalso includes shared memory, including registers and addressable memory,to share data between threads and to store output data.

FIG. 3B illustrates a graphics processor 320 having a tiledarchitecture, according to embodiments described herein. In oneembodiment the graphics processor 320 includes a graphics processingengine cluster 322 having multiple instances of the graphics processingengine 310 of FIG. 3A within a graphics engine tile 310A-310D. Eachgraphics engine tile 310A-310D can be interconnected via a set of tileinterconnects 323A-323F. Each graphics engine tile 310A-310D can also beconnected to a memory module or memory device 326A-326D via memoryinterconnects 325A-325D. The memory devices 326A-326D can use anygraphics memory technology. For example, the memory devices 326A-326Dmay be graphics double data rate (GDDR) memory. The memory devices326A-326D, in one embodiment, are high-bandwidth memory (HBM) modulesthat can be on-die with their respective graphics engine tile 310A-310D.In one embodiment the memory devices 326A-326D are stacked memorydevices that can be stacked on top of their respective graphics enginetile 310A-310D. In one embodiment, each graphics engine tile 310A-310Dand associated memory 326A-326D reside on separate chiplets, which arebonded to a base die or base substrate, as described on further detailin FIGS. 11B-11D.

The graphics processing engine cluster 322 can connect with an on-chipor on-package fabric interconnect 324. The fabric interconnect 324 canenable communication between graphics engine tiles 310A-310D andcomponents such as the video codec 306 and one or more copy engines 304.The copy engines 304 can be used to move data out of, into, and betweenthe memory devices 326A-326D and memory that is external to the graphicsprocessor 320 (e.g., system memory). The fabric interconnect 324 canalso be used to interconnect the graphics engine tiles 310A-310D. Thegraphics processor 320 may optionally include a display controller 302to enable a connection with an external display device 318. The graphicsprocessor may also be configured as a graphics or compute accelerator.In the accelerator configuration, the display controller 302 and displaydevice 318 may be omitted.

The graphics processor 320 can connect to a host system via a hostinterface 328. The host interface 328 can enable communication betweenthe graphics processor 320, system memory, and/or other systemcomponents. The host interface 328 can be, for example a PCI express busor another type of host system interface.

FIG. 3C illustrates a compute accelerator 330, according to embodimentsdescribed herein. The compute accelerator 330 can include architecturalsimilarities with the graphics processor 320 of FIG. 3B and is optimizedfor compute acceleration. A compute engine cluster 332 can include a setof compute engine tiles 340A-340D that include execution logic that isoptimized for parallel or vector-based general-purpose computeoperations. In some embodiments, the compute engine tiles 340A-340D donot include fixed function graphics processing logic, although in oneembodiment one or more of the compute engine tiles 340A-340D can includelogic to perform media acceleration. The compute engine tiles 340A-340Dcan connect to memory 326A-326D via memory interconnects 325A-325D. Thememory 326A-326D and memory interconnects 325A-325D may be similartechnology as in graphics processor 320, or can be different. Thegraphics compute engine tiles 340A-340D can also be interconnected via aset of tile interconnects 323A-323F and may be connected with and/orinterconnected by a fabric interconnect 324. In one embodiment thecompute accelerator 330 includes a large L3 cache 336 that can beconfigured as a device-wide cache. The compute accelerator 330 can alsoconnect to a host processor and memory via a host interface 328 in asimilar manner as the graphics processor 320 of FIG. 3B.

Graphics Processing Engine

FIG. 4 is a block diagram of a graphics processing engine 410 of agraphics processor in accordance with some embodiments. In oneembodiment, the graphics processing engine (GPE) 410 is a version of theGPE 310 shown in FIG. 3A, and may also represent a graphics engine tile310A-310D of FIG. 3B. Elements of FIG. 4 having the same referencenumbers (or names) as the elements of any other figure herein canoperate or function in any manner similar to that described elsewhereherein, but are not limited to such. For example, the 3D pipeline 312and media pipeline 316 of FIG. 3A are illustrated. The media pipeline316 is optional in some embodiments of the GPE 410 and may not beexplicitly included within the GPE 410. For example and in at least oneembodiment, a separate media and/or image processor is coupled to theGPE 410.

In some embodiments, GPE 410 couples with or includes a command streamer403, which provides a command stream to the 3D pipeline 312 and/or mediapipelines 316. In some embodiments, command streamer 403 is coupled withmemory, which can be system memory, or one or more of internal cachememory and shared cache memory. In some embodiments, command streamer403 receives commands from the memory and sends the commands to 3Dpipeline 312 and/or media pipeline 316. The commands are directivesfetched from a ring buffer, which stores commands for the 3D pipeline312 and media pipeline 316. In one embodiment, the ring buffer canadditionally include batch command buffers storing batches of multiplecommands. The commands for the 3D pipeline 312 can also includereferences to data stored in memory, such as but not limited to vertexand geometry data for the 3D pipeline 312 and/or image data and memoryobjects for the media pipeline 316. The 3D pipeline 312 and mediapipeline 316 process the commands and data by performing operations vialogic within the respective pipelines or by dispatching one or moreexecution threads to a graphics core array 414. In one embodiment thegraphics core array 414 include one or more blocks of graphics cores(e.g., graphics core(s) 415A, graphics core(s) 415B), each blockincluding one or more graphics cores. Each graphics core includes a setof graphics execution resources that includes general-purpose andgraphics specific execution logic to perform graphics and computeoperations, as well as fixed function texture processing and/or machinelearning and artificial intelligence acceleration logic.

In various embodiments the 3D pipeline 312 can include fixed functionand programmable logic to process one or more shader programs, such asvertex shaders, geometry shaders, pixel shaders, fragment shaders,compute shaders, or other shader programs, by processing theinstructions and dispatching execution threads to the graphics corearray 414. The graphics core array 414 provides a unified block ofexecution resources for use in processing these shader programs.Multi-purpose execution logic (e.g., execution units) within thegraphics core(s) 415A-414B of the graphic core array 414 includessupport for various 3D API shader languages and can execute multiplesimultaneous execution threads associated with multiple shaders.

In some embodiments, the graphics core array 414 includes executionlogic to perform media functions, such as video and/or image processing.In one embodiment, the execution units include general-purpose logicthat is programmable to perform parallel general-purpose computationaloperations, in addition to graphics processing operations. Thegeneral-purpose logic can perform processing operations in parallel orin conjunction with general-purpose logic within the processor core(s)107 of FIG. 1 or core 202A-202N as in FIG. 2A.

Output data generated by threads executing on the graphics core array414 can output data to memory in a unified return buffer (URB) 418. TheURB 418 can store data for multiple threads. In some embodiments the URB418 may be used to send data between different threads executing on thegraphics core array 414. In some embodiments the URB 418 mayadditionally be used for synchronization between threads on the graphicscore array and fixed function logic within the shared function logic420.

In some embodiments, graphics core array 414 is scalable, such that thearray includes a variable number of graphics cores, each having avariable number of execution units based on the target power andperformance level of GPE 410. In one embodiment the execution resourcesare dynamically scalable, such that execution resources may be enabledor disabled as needed.

The graphics core array 414 couples with shared function logic 420 thatincludes multiple resources that are shared between the graphics coresin the graphics core array. The shared functions within the sharedfunction logic 420 are hardware logic units that provide specializedsupplemental functionality to the graphics core array 414. In variousembodiments, shared function logic 420 includes but is not limited tosampler 421, math 422, and inter-thread communication (ITC) 423 logic.Additionally, some embodiments implement one or more cache(s) 425 withinthe shared function logic 420.

A shared function is implemented at least in a case where the demand fora given specialized function is insufficient for inclusion within thegraphics core array 414. Instead a single instantiation of thatspecialized function is implemented as a stand-alone entity in theshared function logic 420 and shared among the execution resourceswithin the graphics core array 414. The precise set of functions thatare shared between the graphics core array 414 and included within thegraphics core array 414 varies across embodiments. In some embodiments,specific shared functions within the shared function logic 420 that areused extensively by the graphics core array 414 may be included withinshared function logic 416 within the graphics core array 414. In variousembodiments, the shared function logic 416 within the graphics corearray 414 can include some or all logic within the shared function logic420. In one embodiment, all logic elements within the shared functionlogic 420 may be duplicated within the shared function logic 416 of thegraphics core array 414. In one embodiment the shared function logic 420is excluded in favor of the shared function logic 416 within thegraphics core array 414.

Execution Units

FIGS. 5A-5B illustrate thread execution logic 500 including an array ofprocessing elements employed in a graphics processor core according toembodiments described herein. Elements of FIGS. 5A-5B having the samereference numbers (or names) as the elements of any other figure hereincan operate or function in any manner similar to that describedelsewhere herein, but are not limited to such. FIG. 5A-5B illustrates anoverview of thread execution logic 500, which may be representative ofhardware logic illustrated with each sub-core 221A-221F of FIG. 2B. FIG.5A is representative of an execution unit within a general-purposegraphics processor, while FIG. 5B is representative of an execution unitthat may be used within a compute accelerator.

As illustrated in FIG. 5A, in some embodiments thread execution logic500 includes a shader processor 502, a thread dispatcher 504,instruction cache 506, a scalable execution unit array including aplurality of execution units 508A-508N, a sampler 510, shared localmemory 511, a data cache 512, and a data port 514. In one embodiment thescalable execution unit array can dynamically scale by enabling ordisabling one or more execution units (e.g., any of execution units508A, 508B, 508C, 508D, through 508N-1 and 508N) based on thecomputational requirements of a workload. In one embodiment the includedcomponents are interconnected via an interconnect fabric that links toeach of the components. In some embodiments, thread execution logic 500includes one or more connections to memory, such as system memory orcache memory, through one or more of instruction cache 506, data port514, sampler 510, and execution units 508A-508N. In some embodiments,each execution unit (e.g. 508A) is a stand-alone programmablegeneral-purpose computational unit that is capable of executing multiplesimultaneous hardware threads while processing multiple data elements inparallel for each thread. In various embodiments, the array of executionunits 508A-508N is scalable to include any number individual executionunits.

In some embodiments, the execution units 508A-508N are primarily used toexecute shader programs. A shader processor 502 can process the variousshader programs and dispatch execution threads associated with theshader programs via a thread dispatcher 504. In one embodiment thethread dispatcher includes logic to arbitrate thread initiation requestsfrom the graphics and media pipelines and instantiate the requestedthreads on one or more execution unit in the execution units 508A-508N.For example, a geometry pipeline can dispatch vertex, tessellation, orgeometry shaders to the thread execution logic for processing. In someembodiments, thread dispatcher 504 can also process runtime threadspawning requests from the executing shader programs.

In some embodiments, the execution units 508A-508N support aninstruction set that includes native support for many standard 3Dgraphics shader instructions, such that shader programs from graphicslibraries (e.g., Direct 3D and OpenGL) are executed with a minimaltranslation. The execution units support vertex and geometry processing(e.g., vertex programs, geometry programs, vertex shaders), pixelprocessing (e.g., pixel shaders, fragment shaders) and general-purposeprocessing (e.g., compute and media shaders). Each of the executionunits 508A-508N is capable of multi-issue single instruction multipledata (SIMD) execution and multi-threaded operation enables an efficientexecution environment in the face of higher latency memory accesses.Each hardware thread within each execution unit has a dedicatedhigh-bandwidth register file and associated independent thread-state.Execution is multi-issue per clock to pipelines capable of integer,single and double precision floating point operations, SIMD branchcapability, logical operations, transcendental operations, and othermiscellaneous operations. While waiting for data from memory or one ofthe shared functions, dependency logic within the execution units508A-508N causes a waiting thread to sleep until the requested data hasbeen returned. While the waiting thread is sleeping, hardware resourcesmay be devoted to processing other threads. For example, during a delayassociated with a vertex shader operation, an execution unit can performoperations for a pixel shader, fragment shader, or another type ofshader program, including a different vertex shader. Various embodimentscan apply to use execution by use of Single Instruction Multiple Thread(SIMT) as an alternate to use of SIMD or in addition to use of SIMD.Reference to a SIMD core or operation can apply also to SIMT or apply toSIMD in combination with SIMT.

Each execution unit in execution units 508A-508N operates on arrays ofdata elements. The number of data elements is the “execution size,” orthe number of channels for the instruction. An execution channel is alogical unit of execution for data element access, masking, and flowcontrol within instructions. The number of channels may be independentof the number of physical Arithmetic Logic Units (ALUs) or FloatingPoint Units (FPUs) for a particular graphics processor. In someembodiments, execution units 508A-508N support integer andfloating-point data types.

The execution unit instruction set includes SIMD instructions. Thevarious data elements can be stored as a packed data type in a registerand the execution unit will process the various elements based on thedata size of the elements. For example, when operating on a 256-bit widevector, the 256 bits of the vector are stored in a register and theexecution unit operates on the vector as four separate 54-bit packeddata elements (Quad-Word (QW) size data elements), eight separate 32-bitpacked data elements (Double Word (DW) size data elements), sixteenseparate 16-bit packed data elements (Word (W) size data elements), orthirty-two separate 8-bit data elements (byte (B) size data elements).However, different vector widths and register sizes are possible.

In one embodiment one or more execution units can be combined into afused execution unit 509A-509N having thread control logic (507A-507N)that is common to the fused EUs. Multiple EUs can be fused into an EUgroup. Each EU in the fused EU group can be configured to execute aseparate SIMD hardware thread. The number of EUs in a fused EU group canvary according to embodiments. Additionally, various SIMD widths can beperformed per-EU, including but not limited to SIMD8, SIMD16, andSIMD32. Each fused graphics execution unit 509A-509N includes at leasttwo execution units. For example, fused execution unit 509A includes afirst EU 508A, second EU 508B, and thread control logic 507A that iscommon to the first EU 508A and the second EU 508B. The thread controllogic 507A controls threads executed on the fused graphics executionunit 509A, allowing each EU within the fused execution units 509A-509Nto execute using a common instruction pointer register.

One or more internal instruction caches (e.g., 506) are included in thethread execution logic 500 to cache thread instructions for theexecution units. In some embodiments, one or more data caches (e.g.,512) are included to cache thread data during thread execution. Threadsexecuting on the execution logic 500 can also store explicitly manageddata in the shared local memory 511. In some embodiments, a sampler 510is included to provide texture sampling for 3D operations and mediasampling for media operations. In some embodiments, sampler 510 includesspecialized texture or media sampling functionality to process textureor media data during the sampling process before providing the sampleddata to an execution unit.

During execution, the graphics and media pipelines send threadinitiation requests to thread execution logic 500 via thread spawningand dispatch logic. Once a group of geometric objects has been processedand rasterized into pixel data, pixel processor logic (e.g., pixelshader logic, fragment shader logic, etc.) within the shader processor502 is invoked to further compute output information and cause resultsto be written to output surfaces (e.g., color buffers, depth buffers,stencil buffers, etc.). In some embodiments, a pixel shader or fragmentshader calculates the values of the various vertex attributes that areto be interpolated across the rasterized object. In some embodiments,pixel processor logic within the shader processor 502 then executes anapplication programming interface (API)-supplied pixel or fragmentshader program. To execute the shader program, the shader processor 502dispatches threads to an execution unit (e.g., 508A) via threaddispatcher 504. In some embodiments, shader processor 502 uses texturesampling logic in the sampler 510 to access texture data in texture mapsstored in memory. Arithmetic operations on the texture data and theinput geometry data compute pixel color data for each geometricfragment, or discards one or more pixels from further processing.

In some embodiments, the data port 514 provides a memory accessmechanism for the thread execution logic 500 to output processed data tomemory for further processing on a graphics processor output pipeline.In some embodiments, the data port 514 includes or couples to one ormore cache memories (e.g., data cache 512) to cache data for memoryaccess via the data port.

In one embodiment, the execution logic 500 can also include a ray tracer505 that can provide ray tracing acceleration functionality. The raytracer 505 can support a ray tracing instruction set that includesinstructions/functions for ray generation. The ray tracing instructionset can be similar to or different from the ray-tracing instruction setsupported by the ray tracing cores 245 in FIG. 2C.

FIG. 5B illustrates exemplary internal details of an execution unit 508,according to embodiments. A graphics execution unit 508 can include aninstruction fetch unit 537, a general register file array (GRF) 524, anarchitectural register file array (ARF) 526, a thread arbiter 522, asend unit 530, a branch unit 532, a set of SIMD floating point units(FPUs) 534, and in one embodiment a set of dedicated integer SIMD ALUs535. The GRF 524 and ARF 526 includes the set of general register filesand architecture register files associated with each simultaneoushardware thread that may be active in the graphics execution unit 508.In one embodiment, per thread architectural state is maintained in theARF 526, while data used during thread execution is stored in the GRF524. The execution state of each thread, including the instructionpointers for each thread, can be held in thread-specific registers inthe ARF 526.

In one embodiment the graphics execution unit 508 has an architecturethat is a combination of Simultaneous Multi-Threading (SMT) andfine-grained Interleaved Multi-Threading (IMT). The architecture has amodular configuration that can be fine-tuned at design time based on atarget number of simultaneous threads and number of registers perexecution unit, where execution unit resources are divided across logicused to execute multiple simultaneous threads. The number of logicalthreads that may be executed by the graphics execution unit 508 is notlimited to the number of hardware threads, and multiple logical threadscan be assigned to each hardware thread.

In one embodiment, the graphics execution unit 508 can co-issue multipleinstructions, which may each be different instructions. The threadarbiter 522 of the graphics execution unit thread 508 can dispatch theinstructions to one of the send unit 530, branch unit 532, or SIMDFPU(s) 534 for execution. Each execution thread can access 128general-purpose registers within the GRF 524, where each register canstore 32 bytes, accessible as a SIMD 8-element vector of 32-bit dataelements. In one embodiment, each execution unit thread has access to 4Kbytes within the GRF 524, although embodiments are not so limited, andgreater or fewer register resources may be provided in otherembodiments. In one embodiment the graphics execution unit 508 ispartitioned into seven hardware threads that can independently performcomputational operations, although the number of threads per executionunit can also vary according to embodiments. For example, in oneembodiment up to 16 hardware threads are supported. In an embodiment inwhich seven threads may access 4 Kbytes, the GRF 524 can store a totalof 28 Kbytes. Where 16 threads may access 4 Kbytes, the GRF 524 canstore a total of 64 Kbytes. Flexible addressing modes can permitregisters to be addressed together to build effectively wider registersor to represent strided rectangular block data structures.

In one embodiment, memory operations, sampler operations, and otherlonger-latency system communications are dispatched via “send”instructions that are executed by the message passing send unit 530. Inone embodiment, branch instructions are dispatched to a dedicated branchunit 532 to facilitate SIMD divergence and eventual convergence.

In one embodiment the graphics execution unit 508 includes one or moreSIMD floating point units (FPU(s)) 534 to perform floating-pointoperations. In one embodiment, the FPU(s) 534 also support integercomputation. In one embodiment the FPU(s) 534 can SIMD execute up to Mnumber of 32-bit floating-point (or integer) operations, or SIMD executeup to 2M 16-bit integer or 16-bit floating-point operations. In oneembodiment, at least one of the FPU(s) provides extended math capabilityto support high-throughput transcendental math functions and doubleprecision 54-bit floating-point. In some embodiments, a set of 8-bitinteger SIMD ALUs 535 are also present, and may be specificallyoptimized to perform operations associated with machine learningcomputations.

In one embodiment, arrays of multiple instances of the graphicsexecution unit 508 can be instantiated in a graphics sub-core grouping(e.g., a sub-slice). For scalability, product architects can choose theexact number of execution units per sub-core grouping. In one embodimentthe execution unit 508 can execute instructions across a plurality ofexecution channels. In a further embodiment, each thread executed on thegraphics execution unit 508 is executed on a different channel.

FIG. 6 illustrates an additional execution unit 600, according to anembodiment. The execution unit 600 may be a compute-optimized executionunit for use in, for example, a compute engine tile 340A-340D as in FIG.3C, but is not limited as such. Variants of the execution unit 600 mayalso be used in a graphics engine tile 310A-310D as in FIG. 3B. In oneembodiment, the execution unit 600 includes a thread control unit 601, athread state unit 602, an instruction fetch/prefetch unit 603, and aninstruction decode unit 604. The execution unit 600 additionallyincludes a register file 606 that stores registers that can be assignedto hardware threads within the execution unit. The execution unit 600additionally includes a send unit 607 and a branch unit 608. In oneembodiment, the send unit 607 and branch unit 608 can operate similarlyas the send unit 530 and a branch unit 532 of the graphics executionunit 508 of FIG. 5B.

The execution unit 600 also includes a compute unit 610 that includesmultiple different types of functional units. In one embodiment thecompute unit 610 includes an ALU unit 611 that includes an array ofarithmetic logic units. The ALU unit 611 can be configured to perform64-bit, 32-bit, and 16-bit integer and floating point operations.Integer and floating point operations may be performed simultaneously.The compute unit 610 can also include a systolic array 612, and a mathunit 613. The systolic array 612 includes a W wide and D deep network ofdata processing units that can be used to perform vector or otherdata-parallel operations in a systolic manner. In one embodiment thesystolic array 612 can be configured to perform matrix operations, suchas matrix dot product operations. In one embodiment the systolic array612 support 16-bit floating point operations, as well as 8-bit and 4-bitinteger operations. In one embodiment the systolic array 612 can beconfigured to accelerate machine learning operations. In suchembodiments, the systolic array 612 can be configured with support forthe bfloat 16-bit floating point format. In one embodiment, a math unit613 can be included to perform a specific subset of mathematicaloperations in an efficient and lower-power manner than then ALU unit611. The math unit 613 can include a variant of math logic that may befound in shared function logic of a graphics processing engine providedby other embodiments (e.g., math logic 422 of the shared function logic420 of FIG. 4). In one embodiment the math unit 613 can be configured toperform 32-bit and 64-bit floating point operations.

The thread control unit 601 includes logic to control the execution ofthreads within the execution unit. The thread control unit 601 caninclude thread arbitration logic to start, stop, and preempt executionof threads within the execution unit 600. The thread state unit 602 canbe used to store thread state for threads assigned to execute on theexecution unit 600. Storing the thread state within the execution unit600 enables the rapid pre-emption of threads when those threads becomeblocked or idle. The instruction fetch/prefetch unit 603 can fetchinstructions from an instruction cache of higher level execution logic(e.g., instruction cache 506 as in FIG. 5A). The instructionfetch/prefetch unit 603 can also issue prefetch requests forinstructions to be loaded into the instruction cache based on ananalysis of currently executing threads. The instruction decode unit 604can be used to decode instructions to be executed by the compute units.In one embodiment, the instruction decode unit 604 can be used as asecondary decoder to decode complex instructions into constituentmicro-operations.

The execution unit 600 additionally includes a register file 606 thatcan be used by hardware threads executing on the execution unit 600.Registers in the register file 606 can be divided across the logic usedto execute multiple simultaneous threads within the compute unit 610 ofthe execution unit 600. The number of logical threads that may beexecuted by the graphics execution unit 600 is not limited to the numberof hardware threads, and multiple logical threads can be assigned toeach hardware thread. The size of the register file 606 can vary acrossembodiments based on the number of supported hardware threads. In oneembodiment, register renaming may be used to dynamically allocateregisters to hardware threads.

FIG. 7 is a block diagram illustrating graphics processor instructionformats 700 according to some embodiments. In one or more embodiment,the graphics processor execution units support an instruction set havinginstructions in multiple formats. The solid lined boxes illustrate thecomponents that are generally included in an execution unit instruction,while the dashed lines include components that are optional or that areonly included in a sub-set of the instructions. In some embodiments,instruction format 700 described and illustrated are macro-instructions,in that they are instructions supplied to the execution unit, as opposedto micro-operations resulting from instruction decode once theinstruction is processed.

In some embodiments, the graphics processor execution units nativelysupport instructions in a 128-bit instruction format 710. A 64-bitcompacted instruction format 730 is available for some instructionsbased on the selected instruction, instruction options, and number ofoperands. The native 128-bit instruction format 710 provides access toall instruction options, while some options and operations arerestricted in the 64-bit format 730. The native instructions availablein the 64-bit format 730 vary by embodiment. In some embodiments, theinstruction is compacted in part using a set of index values in an indexfield 713. The execution unit hardware references a set of compactiontables based on the index values and uses the compaction table outputsto reconstruct a native instruction in the 128-bit instruction format710. Other sizes and formats of instruction can be used.

For each format, instruction opcode 712 defines the operation that theexecution unit is to perform. The execution units execute eachinstruction in parallel across the multiple data elements of eachoperand. For example, in response to an add instruction the executionunit performs a simultaneous add operation across each color channelrepresenting a texture element or picture element. By default, theexecution unit performs each instruction across all data channels of theoperands. In some embodiments, instruction control field 714 enablescontrol over certain execution options, such as channels selection(e.g., predication) and data channel order (e.g., swizzle). Forinstructions in the 128-bit instruction format 710 an exec-size field716 limits the number of data channels that will be executed inparallel. In some embodiments, exec-size field 716 is not available foruse in the 64-bit compact instruction format 730.

Some execution unit instructions have up to three operands including twosource operands, src0 720, src1 722, and one destination 718. In someembodiments, the execution units support dual destination instructions,where one of the destinations is implied. Data manipulation instructionscan have a third source operand (e.g., SRC2 724), where the instructionopcode 712 determines the number of source operands. An instruction'slast source operand can be an immediate (e.g., hard-coded) value passedwith the instruction.

In some embodiments, the 128-bit instruction format 710 includes anaccess/address mode field 726 specifying, for example, whether directregister addressing mode or indirect register addressing mode is used.When direct register addressing mode is used, the register address ofone or more operands is directly provided by bits in the instruction.

In some embodiments, the 128-bit instruction format 710 includes anaccess/address mode field 726, which specifies an address mode and/or anaccess mode for the instruction. In one embodiment the access mode isused to define a data access alignment for the instruction. Someembodiments support access modes including a 16-byte aligned access modeand a 1-byte aligned access mode, where the byte alignment of the accessmode determines the access alignment of the instruction operands. Forexample, when in a first mode, the instruction may use byte-alignedaddressing for source and destination operands and when in a secondmode, the instruction may use 16-byte-aligned addressing for all sourceand destination operands.

In one embodiment, the address mode portion of the access/address modefield 726 determines whether the instruction is to use direct orindirect addressing. When direct register addressing mode is used bitsin the instruction directly provide the register address of one or moreoperands. When indirect register addressing mode is used, the registeraddress of one or more operands may be computed based on an addressregister value and an address immediate field in the instruction.

In some embodiments instructions are grouped based on opcode 712bit-fields to simplify Opcode decode 740. For an 8-bit opcode, bits 4,5, and 6 allow the execution unit to determine the type of opcode. Theprecise opcode grouping shown is merely an example. In some embodiments,a move and logic opcode group 742 includes data movement and logicinstructions (e.g., move (mov), compare (cmp)). In some embodiments,move and logic group 742 shares the five most significant bits (MSB),where move (mov) instructions are in the form of 0000xxxxb and logicinstructions are in the form of 0001xxxxb. A flow control instructiongroup 744 (e.g., call, jump (jmp)) includes instructions in the form of0010xxxxb (e.g., 0x20). A miscellaneous instruction group 746 includes amix of instructions, including synchronization instructions (e.g., wait,send) in the form of 0011xxxxb (e.g., 0x30). A parallel math instructiongroup 748 includes component-wise arithmetic instructions (e.g., add,multiply (mul)) in the form of 0100xxxxb (e.g., 0x40). The parallel mathgroup 748 performs the arithmetic operations in parallel across datachannels. The vector math group 750 includes arithmetic instructions(e.g., dp4) in the form of 0101xxxxb (e.g., 0x50). The vector math groupperforms arithmetic such as dot product calculations on vector operands.The illustrated opcode decode 740, in one embodiment, can be used todetermine which portion of an execution unit will be used to execute adecoded instruction. For example, some instructions may be designated assystolic instructions that will be performed by a systolic array. Otherinstructions, such as ray-tracing instructions (not shown) can be routedto a ray-tracing core or ray-tracing logic within a slice or partitionof execution logic.

Graphics Pipeline

FIG. 8 is a block diagram of another embodiment of a graphics processor800. Elements of FIG. 8 having the same reference numbers (or names) asthe elements of any other figure herein can operate or function in anymanner similar to that described elsewhere herein, but are not limitedto such.

In some embodiments, graphics processor 800 includes a geometry pipeline820, a media pipeline 830, a display engine 840, thread execution logic850, and a render output pipeline 870. In some embodiments, graphicsprocessor 800 is a graphics processor within a multi-core processingsystem that includes one or more general-purpose processing cores. Thegraphics processor is controlled by register writes to one or morecontrol registers (not shown) or via commands issued to graphicsprocessor 800 via a ring interconnect 802. In some embodiments, ringinterconnect 802 couples graphics processor 800 to other processingcomponents, such as other graphics processors or general-purposeprocessors. Commands from ring interconnect 802 are interpreted by acommand streamer 803, which supplies instructions to individualcomponents of the geometry pipeline 820 or the media pipeline 830.

In some embodiments, command streamer 803 directs the operation of avertex fetcher 805 that reads vertex data from memory and executesvertex-processing commands provided by command streamer 803. In someembodiments, vertex fetcher 805 provides vertex data to a vertex shader807, which performs coordinate space transformation and lightingoperations to each vertex. In some embodiments, vertex fetcher 805 andvertex shader 807 execute vertex-processing instructions by dispatchingexecution threads to execution units 852A-852B via a thread dispatcher831.

In some embodiments, execution units 852A-852B are an array of vectorprocessors having an instruction set for performing graphics and mediaoperations. In some embodiments, execution units 852A-852B have anattached L1 cache 851 that is specific for each array or shared betweenthe arrays. The cache can be configured as a data cache, an instructioncache, or a single cache that is partitioned to contain data andinstructions in different partitions.

In some embodiments, geometry pipeline 820 includes tessellationcomponents to perform hardware-accelerated tessellation of 3D objects.In some embodiments, a programmable hull shader 811 configures thetessellation operations. A programmable domain shader 817 providesback-end evaluation of tessellation output. A tessellator 813 operatesat the direction of hull shader 811 and contains special purpose logicto generate a set of detailed geometric objects based on a coarsegeometric model that is provided as input to geometry pipeline 820. Insome embodiments, if tessellation is not used, tessellation components(e.g., hull shader 811, tessellator 813, and domain shader 817) can bebypassed.

In some embodiments, complete geometric objects can be processed by ageometry shader 819 via one or more threads dispatched to executionunits 852A-852B, or can proceed directly to the clipper 829. In someembodiments, the geometry shader operates on entire geometric objects,rather than vertices or patches of vertices as in previous stages of thegraphics pipeline. If the tessellation is disabled the geometry shader819 receives input from the vertex shader 807. In some embodiments,geometry shader 819 is programmable by a geometry shader program toperform geometry tessellation if the tessellation units are disabled.

Before rasterization, a clipper 829 processes vertex data. The clipper829 may be a fixed function clipper or a programmable clipper havingclipping and geometry shader functions. In some embodiments, arasterizer and depth test component 873 in the render output pipeline870 dispatches pixel shaders to convert the geometric objects into perpixel representations. In some embodiments, pixel shader logic isincluded in thread execution logic 850. In some embodiments, anapplication can bypass the rasterizer and depth test component 873 andaccess un-rasterized vertex data via a stream out unit 823.

The graphics processor 800 has an interconnect bus, interconnect fabric,or some other interconnect mechanism that allows data and messagepassing amongst the major components of the processor. In someembodiments, execution units 852A-852B and associated logic units (e.g.,L1 cache 851, sampler 854, texture cache 858, etc.) interconnect via adata port 856 to perform memory access and communicate with renderoutput pipeline components of the processor. In some embodiments,sampler 854, caches 851, 858 and execution units 852A-852B each haveseparate memory access paths. In one embodiment the texture cache 858can also be configured as a sampler cache.

In some embodiments, render output pipeline 870 contains a rasterizerand depth test component 873 that converts vertex-based objects into anassociated pixel-based representation. In some embodiments, therasterizer logic includes a windower/masker unit to perform fixedfunction triangle and line rasterization. An associated render cache 878and depth cache 879 are also available in some embodiments. A pixeloperations component 877 performs pixel-based operations on the data,though in some instances, pixel operations associated with 2D operations(e.g. bit block image transfers with blending) are performed by the 2Dengine 841, or substituted at display time by the display controller 843using overlay display planes. In some embodiments, a shared L3 cache 875is available to all graphics components, allowing the sharing of datawithout the use of main system memory.

In some embodiments, graphics processor media pipeline 830 includes amedia engine 837 and a video front-end 834. In some embodiments, videofront-end 834 receives pipeline commands from the command streamer 803.In some embodiments, media pipeline 830 includes a separate commandstreamer. In some embodiments, video front-end 834 processes mediacommands before sending the command to the media engine 837. In someembodiments, media engine 837 includes thread spawning functionality tospawn threads for dispatch to thread execution logic 850 via threaddispatcher 831.

In some embodiments, graphics processor 800 includes a display engine840. In some embodiments, display engine 840 is external to processor800 and couples with the graphics processor via the ring interconnect802, or some other interconnect bus or fabric. In some embodiments,display engine 840 includes a 2D engine 841 and a display controller843. In some embodiments, display engine 840 contains special purposelogic capable of operating independently of the 3D pipeline. In someembodiments, display controller 843 couples with a display device (notshown), which may be a system integrated display device, as in a laptopcomputer, or an external display device attached via a display deviceconnector.

In some embodiments, the geometry pipeline 820 and media pipeline 830are configurable to perform operations based on multiple graphics andmedia programming interfaces and are not specific to any one applicationprogramming interface (API). In some embodiments, driver software forthe graphics processor translates API calls that are specific to aparticular graphics or media library into commands that can be processedby the graphics processor. In some embodiments, support is provided forthe Open Graphics Library (OpenGL), Open Computing Language (OpenCL),and/or Vulkan graphics and compute API, all from the Khronos Group. Insome embodiments, support may also be provided for the Direct3D libraryfrom the Microsoft Corporation. In some embodiments, a combination ofthese libraries may be supported. Support may also be provided for theOpen Source Computer Vision Library (OpenCV). A future API with acompatible 3D pipeline would also be supported if a mapping can be madefrom the pipeline of the future API to the pipeline of the graphicsprocessor.

Graphics Pipeline Programming

FIG. 9A is a block diagram illustrating a graphics processor commandformat 900 according to some embodiments. FIG. 9B is a block diagramillustrating a graphics processor command sequence 910 according to anembodiment. The solid lined boxes in FIG. 9A illustrate the componentsthat are generally included in a graphics command while the dashed linesinclude components that are optional or that are only included in asub-set of the graphics commands. The exemplary graphics processorcommand format 900 of FIG. 9A includes data fields to identify a client902, a command operation code (opcode) 904, and data 906 for thecommand. A sub-opcode 905 and a command size 908 are also included insome commands.

In some embodiments, client 902 specifies the client unit of thegraphics device that processes the command data. In some embodiments, agraphics processor command parser examines the client field of eachcommand to condition the further processing of the command and route thecommand data to the appropriate client unit. In some embodiments, thegraphics processor client units include a memory interface unit, arender unit, a 2D unit, a 3D unit, and a media unit. Each client unithas a corresponding processing pipeline that processes the commands.Once the command is received by the client unit, the client unit readsthe opcode 904 and, if present, sub-opcode 905 to determine theoperation to perform. The client unit performs the command usinginformation in data field 906. For some commands an explicit commandsize 908 is expected to specify the size of the command. In someembodiments, the command parser automatically determines the size of atleast some of the commands based on the command opcode. In someembodiments commands are aligned via multiples of a double word. Othercommand formats can be used.

The flow diagram in FIG. 9B illustrates an exemplary graphics processorcommand sequence 910. In some embodiments, software or firmware of adata processing system that features an embodiment of a graphicsprocessor uses a version of the command sequence shown to set up,execute, and terminate a set of graphics operations. A sample commandsequence is shown and described for purposes of example only asembodiments are not limited to these specific commands or to thiscommand sequence. Moreover, the commands may be issued as batch ofcommands in a command sequence, such that the graphics processor willprocess the sequence of commands in at least partially concurrence.

In some embodiments, the graphics processor command sequence 910 maybegin with a pipeline flush command 912 to cause any active graphicspipeline to complete the currently pending commands for the pipeline. Insome embodiments, the 3D pipeline 922 and the media pipeline 924 do notoperate concurrently. The pipeline flush is performed to cause theactive graphics pipeline to complete any pending commands. In responseto a pipeline flush, the command parser for the graphics processor willpause command processing until the active drawing engines completepending operations and the relevant read caches are invalidated.Optionally, any data in the render cache that is marked ‘dirty’ can beflushed to memory. In some embodiments, pipeline flush command 912 canbe used for pipeline synchronization or before placing the graphicsprocessor into a low power state.

In some embodiments, a pipeline select command 913 is used when acommand sequence requires the graphics processor to explicitly switchbetween pipelines. In some embodiments, a pipeline select command 913 isrequired only once within an execution context before issuing pipelinecommands unless the context is to issue commands for both pipelines. Insome embodiments, a pipeline flush command 912 is required immediatelybefore a pipeline switch via the pipeline select command 913.

In some embodiments, a pipeline control command 914 configures agraphics pipeline for operation and is used to program the 3D pipeline922 and the media pipeline 924. In some embodiments, pipeline controlcommand 914 configures the pipeline state for the active pipeline. Inone embodiment, the pipeline control command 914 is used for pipelinesynchronization and to clear data from one or more cache memories withinthe active pipeline before processing a batch of commands.

In some embodiments, return buffer state commands 916 are used toconfigure a set of return buffers for the respective pipelines to writedata. Some pipeline operations require the allocation, selection, orconfiguration of one or more return buffers into which the operationswrite intermediate data during processing. In some embodiments, thegraphics processor also uses one or more return buffers to store outputdata and to perform cross thread communication. In some embodiments, thereturn buffer state 916 includes selecting the size and number of returnbuffers to use for a set of pipeline operations.

The remaining commands in the command sequence differ based on theactive pipeline for operations. Based on a pipeline determination 920,the command sequence is tailored to the 3D pipeline 922 beginning withthe 3D pipeline state 930 or the media pipeline 924 beginning at themedia pipeline state 940.

The commands to configure the 3D pipeline state 930 include 3D statesetting commands for vertex buffer state, vertex element state, constantcolor state, depth buffer state, and other state variables that are tobe configured before 3D primitive commands are processed. The values ofthese commands are determined at least in part based on the particular3D API in use. In some embodiments, 3D pipeline state 930 commands arealso able to selectively disable or bypass certain pipeline elements ifthose elements will not be used.

In some embodiments, 3D primitive 932 command is used to submit 3Dprimitives to be processed by the 3D pipeline. Commands and associatedparameters that are passed to the graphics processor via the 3Dprimitive 932 command are forwarded to the vertex fetch function in thegraphics pipeline. The vertex fetch function uses the 3D primitive 932command data to generate vertex data structures. The vertex datastructures are stored in one or more return buffers. In someembodiments, 3D primitive 932 command is used to perform vertexoperations on 3D primitives via vertex shaders. To process vertexshaders, 3D pipeline 922 dispatches shader execution threads to graphicsprocessor execution units.

In some embodiments, 3D pipeline 922 is triggered via an execute 934command or event. In some embodiments, a register write triggers commandexecution. In some embodiments execution is triggered via a ‘go’ or‘kick’ command in the command sequence. In one embodiment, commandexecution is triggered using a pipeline synchronization command to flushthe command sequence through the graphics pipeline. The 3D pipeline willperform geometry processing for the 3D primitives. Once operations arecomplete, the resulting geometric objects are rasterized and the pixelengine colors the resulting pixels. Additional commands to control pixelshading and pixel back end operations may also be included for thoseoperations.

In some embodiments, the graphics processor command sequence 910 followsthe media pipeline 924 path when performing media operations. Ingeneral, the specific use and manner of programming for the mediapipeline 924 depends on the media or compute operations to be performed.Specific media decode operations may be offloaded to the media pipelineduring media decode. In some embodiments, the media pipeline can also bebypassed and media decode can be performed in whole or in part usingresources provided by one or more general-purpose processing cores. Inone embodiment, the media pipeline also includes elements forgeneral-purpose graphics processor unit (GPGPU) operations, where thegraphics processor is used to perform SIMD vector operations usingcomputational shader programs that are not explicitly related to therendering of graphics primitives.

In some embodiments, media pipeline 924 is configured in a similarmanner as the 3D pipeline 922. A set of commands to configure the mediapipeline state 940 are dispatched or placed into a command queue beforethe media object commands 942. In some embodiments, commands for themedia pipeline state 940 include data to configure the media pipelineelements that will be used to process the media objects. This includesdata to configure the video decode and video encode logic within themedia pipeline, such as encode or decode format. In some embodiments,commands for the media pipeline state 940 also support the use of one ormore pointers to “indirect” state elements that contain a batch of statesettings.

In some embodiments, media object commands 942 supply pointers to mediaobjects for processing by the media pipeline. The media objects includememory buffers containing video data to be processed. In someembodiments, all media pipeline states must be valid before issuing amedia object command 942. Once the pipeline state is configured andmedia object commands 942 are queued, the media pipeline 924 istriggered via an execute command 944 or an equivalent execute event(e.g., register write). Output from media pipeline 924 may then be postprocessed by operations provided by the 3D pipeline 922 or the mediapipeline 924. In some embodiments, GPGPU operations are configured andexecuted in a similar manner as media operations.

Graphics Software Architecture

FIG. 10 illustrates an exemplary graphics software architecture for adata processing system 1000 according to some embodiments. In someembodiments, software architecture includes a 3D graphics application1010, an operating system 1020, and at least one processor 1030. In someembodiments, processor 1030 includes a graphics processor 1032 and oneor more general-purpose processor core(s) 1034. The graphics application1010 and operating system 1020 each execute in the system memory 1050 ofthe data processing system.

In some embodiments, 3D graphics application 1010 contains one or moreshader programs including shader instructions 1012. The shader languageinstructions may be in a high-level shader language, such as theHigh-Level Shader Language (HLSL) of Direct3D, the OpenGL ShaderLanguage (GLSL), and so forth. The application also includes executableinstructions 1014 in a machine language suitable for execution by thegeneral-purpose processor core 1034. The application also includesgraphics objects 1016 defined by vertex data.

In some embodiments, operating system 1020 is a Microsoft® Windows®operating system from the Microsoft Corporation, a proprietary UNIX-likeoperating system, or an open source UNIX-like operating system using avariant of the Linux kernel. The operating system 1020 can support agraphics API 1022 such as the Direct3D API, the OpenGL API, or theVulkan API. When the Direct3D API is in use, the operating system 1020uses a front-end shader compiler 1024 to compile any shader instructions1012 in HLSL into a lower-level shader language. The compilation may bea just-in-time (JIT) compilation or the application can perform shaderpre-compilation. In some embodiments, high-level shaders are compiledinto low-level shaders during the compilation of the 3D graphicsapplication 1010. In some embodiments, the shader instructions 1012 areprovided in an intermediate form, such as a version of the StandardPortable Intermediate Representation (SPIR) used by the Vulkan API.

In some embodiments, user mode graphics driver 1026 contains a back-endshader compiler 1027 to convert the shader instructions 1012 into ahardware specific representation. When the OpenGL API is in use, shaderinstructions 1012 in the GLSL high-level language are passed to a usermode graphics driver 1026 for compilation. In some embodiments, usermode graphics driver 1026 uses operating system kernel mode functions1028 to communicate with a kernel mode graphics driver 1029. In someembodiments, kernel mode graphics driver 1029 communicates with graphicsprocessor 1032 to dispatch commands and instructions.

IP Core Implementations

One or more aspects of at least one embodiment may be implemented byrepresentative code stored on a machine-readable medium which representsand/or defines logic within an integrated circuit such as a processor.For example, the machine-readable medium may include instructions whichrepresent various logic within the processor. When read by a machine,the instructions may cause the machine to fabricate the logic to performthe techniques described herein. Such representations, known as “IPcores,” are reusable units of logic for an integrated circuit that maybe stored on a tangible, machine-readable medium as a hardware modelthat describes the structure of the integrated circuit. The hardwaremodel may be supplied to various customers or manufacturing facilities,which load the hardware model on fabrication machines that manufacturethe integrated circuit. The integrated circuit may be fabricated suchthat the circuit performs operations described in association with anyof the embodiments described herein.

FIG. 11A is a block diagram illustrating an IP core development system1100 that may be used to manufacture an integrated circuit to performoperations according to an embodiment. The IP core development system1100 may be used to generate modular, re-usable designs that can beincorporated into a larger design or used to construct an entireintegrated circuit (e.g., an SOC integrated circuit). A design facility1130 can generate a software simulation 1110 of an IP core design in ahigh-level programming language (e.g., C/C++). The software simulation1110 can be used to design, test, and verify the behavior of the IP coreusing a simulation model 1112. The simulation model 1112 may includefunctional, behavioral, and/or timing simulations. A register transferlevel (RTL) design 1115 can then be created or synthesized from thesimulation model 1112. The RTL design 1115 is an abstraction of thebehavior of the integrated circuit that models the flow of digitalsignals between hardware registers, including the associated logicperformed using the modeled digital signals. In addition to an RTLdesign 1115, lower-level designs at the logic level or transistor levelmay also be created, designed, or synthesized. Thus, the particulardetails of the initial design and simulation may vary.

The RTL design 1115 or equivalent may be further synthesized by thedesign facility into a hardware model 1120, which may be in a hardwaredescription language (HDL), or some other representation of physicaldesign data. The HDL may be further simulated or tested to verify the IPcore design. The IP core design can be stored for delivery to a 3^(rd)party fabrication facility 1165 using non-volatile memory 1140 (e.g.,hard disk, flash memory, or any non-volatile storage medium).Alternatively, the IP core design may be transmitted (e.g., via theInternet) over a wired connection 1150 or wireless connection 1160. Thefabrication facility 1165 may then fabricate an integrated circuit thatis based at least in part on the IP core design. The fabricatedintegrated circuit can be configured to perform operations in accordancewith at least one embodiment described herein.

FIG. 11B illustrates a cross-section side view of an integrated circuitpackage assembly 1170, according to some embodiments described herein.The integrated circuit package assembly 1170 illustrates animplementation of one or more processor or accelerator devices asdescribed herein. The package assembly 1170 includes multiple units ofhardware logic 1172, 1174 connected to a substrate 1180. The logic 1172,1174 may be implemented at least partly in configurable logic orfixed-functionality logic hardware, and can include one or more portionsof any of the processor core(s), graphics processor(s), or otheraccelerator devices described herein. Each unit of logic 1172, 1174 canbe implemented within a semiconductor die and coupled with the substrate1180 via an interconnect structure 1173. The interconnect structure 1173may be configured to route electrical signals between the logic 1172,1174 and the substrate 1180, and can include interconnects such as, butnot limited to bumps or pillars. In some embodiments, the interconnectstructure 1173 may be configured to route electrical signals such as,for example, input/output (I/O) signals and/or power or ground signalsassociated with the operation of the logic 1172, 1174. In someembodiments, the substrate 1180 is an epoxy-based laminate substrate.The substrate 1180 may include other suitable types of substrates inother embodiments. The package assembly 1170 can be connected to otherelectrical devices via a package interconnect 1183. The packageinterconnect 1183 may be coupled to a surface of the substrate 1180 toroute electrical signals to other electrical devices, such as amotherboard, other chipset, or multi-chip module.

In some embodiments, the units of logic 1172, 1174 are electricallycoupled with a bridge 1182 that is configured to route electricalsignals between the logic 1172, 1174. The bridge 1182 may be a denseinterconnect structure that provides a route for electrical signals. Thebridge 1182 may include a bridge substrate composed of glass or asuitable semiconductor material. Electrical routing features can beformed on the bridge substrate to provide a chip-to-chip connectionbetween the logic 1172, 1174.

Although two units of logic 1172, 1174 and a bridge 1182 areillustrated, embodiments described herein may include more or fewerlogic units on one or more dies. The one or more dies may be connectedby zero or more bridges, as the bridge 1182 may be excluded when thelogic is included on a single die. Alternatively, multiple dies or unitsof logic can be connected by one or more bridges. Additionally, multiplelogic units, dies, and bridges can be connected together in otherpossible configurations, including three-dimensional configurations.

FIG. 11C illustrates a package assembly 1190 that includes multipleunits of hardware logic chiplets connected to a substrate 1180 (e.g.,base die). A graphics processing unit, parallel processor, and/orcompute accelerator as described herein can be composed from diversesilicon chiplets that are separately manufactured. In this context, achiplet is an at least partially packaged integrated circuit thatincludes distinct units of logic that can be assembled with otherchiplets into a larger package. A diverse set of chiplets with differentIP core logic can be assembled into a single device. Additionally thechiplets can be integrated into a base die or base chiplet using activeinterposer technology. The concepts described herein enable theinterconnection and communication between the different forms of IPwithin the GPU. IP cores can be manufactured using different processtechnologies and composed during manufacturing, which avoids thecomplexity of converging multiple IPs, especially on a large SoC withseveral flavors IPs, to the same manufacturing process. Enabling the useof multiple process technologies improves the time to market andprovides a cost-effective way to create multiple product SKUs.Additionally, the disaggregated IPs are more amenable to being powergated independently, components that are not in use on a given workloadcan be powered off, reducing overall power consumption.

The hardware logic chiplets can include special purpose hardware logicchiplets 1172, logic or I/O chiplets 1174, and/or memory chiplets 1175.The hardware logic chiplets 1172 and logic or I/O chiplets 1174 may beimplemented at least partly in configurable logic or fixed-functionalitylogic hardware and can include one or more portions of any of theprocessor core(s), graphics processor(s), parallel processors, or otheraccelerator devices described herein. The memory chiplets 1175 can beDRAM (e.g., GDDR, HBM) memory or cache (SRAM) memory.

Each chiplet can be fabricated as separate semiconductor die and coupledwith the substrate 1180 via an interconnect structure 1173. Theinterconnect structure 1173 may be configured to route electricalsignals between the various chiplets and logic within the substrate1180. The interconnect structure 1173 can include interconnects such as,but not limited to bumps or pillars. In some embodiments, theinterconnect structure 1173 may be configured to route electricalsignals such as, for example, input/output (I/O) signals and/or power orground signals associated with the operation of the logic, I/O andmemory chiplets.

In some embodiments, the substrate 1180 is an epoxy-based laminatesubstrate. The substrate 1180 may include other suitable types ofsubstrates in other embodiments. The package assembly 1190 can beconnected to other electrical devices via a package interconnect 1183.The package interconnect 1183 may be coupled to a surface of thesubstrate 1180 to route electrical signals to other electrical devices,such as a motherboard, other chipset, or multi-chip module.

In some embodiments, a logic or I/O chiplet 1174 and a memory chiplet1175 can be electrically coupled via a bridge 1187 that is configured toroute electrical signals between the logic or I/O chiplet 1174 and amemory chiplet 1175. The bridge 1187 may be a dense interconnectstructure that provides a route for electrical signals. The bridge 1187may include a bridge substrate composed of glass or a suitablesemiconductor material. Electrical routing features can be formed on thebridge substrate to provide a chip-to-chip connection between the logicor I/O chiplet 1174 and a memory chiplet 1175. The bridge 1187 may alsobe referred to as a silicon bridge or an interconnect bridge. Forexample, the bridge 1187, in some embodiments, is an Embedded Multi-dieInterconnect Bridge (EMIB). In some embodiments, the bridge 1187 maysimply be a direct connection from one chiplet to another chiplet.

The substrate 1180 can include hardware components for I/O 1191, cachememory 1192, and other hardware logic 1193. A fabric 1185 can beembedded in the substrate 1180 to enable communication between thevarious logic chiplets and the logic 1191, 1193 within the substrate1180. In one embodiment, the I/O 1191, fabric 1185, cache, bridge, andother hardware logic 1193 can be integrated into a base die that islayered on top of the substrate 1180.

In various embodiments a package assembly 1190 can include fewer orgreater number of components and chiplets that are interconnected by afabric 1185 or one or more bridges 1187. The chiplets within the packageassembly 1190 may be arranged in a 3D or 2.5D arrangement. In general,bridge structures 1187 may be used to facilitate a point to pointinterconnect between, for example, logic or I/O chiplets and memorychiplets. The fabric 1185 can be used to interconnect the various logicand/or I/O chiplets (e.g., chiplets 1172, 1174, 1191, 1193). with otherlogic and/or I/O chiplets. In one embodiment, the cache memory 1192within the substrate can act as a global cache for the package assembly1190, part of a distributed global cache, or as a dedicated cache forthe fabric 1185.

FIG. 11D illustrates a package assembly 1194 including interchangeablechiplets 1195, according to an embodiment. The interchangeable chiplets1195 can be assembled into standardized slots on one or more basechiplets 1196, 1198. The base chiplets 1196, 1198 can be coupled via abridge interconnect 1197, which can be similar to the other bridgeinterconnects described herein and may be, for example, an EMIB. Memorychiplets can also be connected to logic or I/O chiplets via a bridgeinterconnect. I/O and logic chiplets can communicate via an interconnectfabric. The base chiplets can each support one or more slots in astandardized format for one of logic or I/O or memory/cache.

In one embodiment, SRAM and power delivery circuits can be fabricatedinto one or more of the base chiplets 1196, 1198, which can befabricated using a different process technology relative to theinterchangeable chiplets 1195 that are stacked on top of the basechiplets. For example, the base chiplets 1196, 1198 can be fabricatedusing a larger process technology, while the interchangeable chipletscan be manufactured using a smaller process technology. One or more ofthe interchangeable chiplets 1195 may be memory (e.g., DRAM) chiplets.Different memory densities can be selected for the package assembly 1194based on the power, and/or performance targeted for the product thatuses the package assembly 1194. Additionally, logic chiplets with adifferent number of type of functional units can be selected at time ofassembly based on the power, and/or performance targeted for theproduct. Additionally, chiplets containing IP logic cores of differingtypes can be inserted into the interchangeable chiplet slots, enablinghybrid processor designs that can mix and match different technology IPblocks.

Exemplary System on a Chip Integrated Circuit

FIGS. 12-13 illustrate exemplary integrated circuits and associatedgraphics processors that may be fabricated using one or more IP cores,according to various embodiments described herein. In addition to whatis illustrated, other logic and circuits may be included, includingadditional graphics processors/cores, peripheral interface controllers,or general-purpose processor cores.

FIG. 12 is a block diagram illustrating an exemplary system on a chipintegrated circuit 1200 that may be fabricated using one or more IPcores, according to an embodiment. Exemplary integrated circuit 1200includes one or more application processor(s) 1205 (e.g., CPUs), atleast one graphics processor 1210, and may additionally include an imageprocessor 1215 and/or a video processor 1220, any of which may be amodular IP core from the same or multiple different design facilities.Integrated circuit 1200 includes peripheral or bus logic including a USBcontroller 1225, UART controller 1230, an SPI/SDIO controller 1235, andan I²S/I²C controller 1240. Additionally, the integrated circuit caninclude a display device 1245 coupled to one or more of ahigh-definition multimedia interface (HDMI) controller 1250 and a mobileindustry processor interface (MIPI) display interface 1255. Storage maybe provided by a flash memory subsystem 1260 including flash memory anda flash memory controller. Memory interface may be provided via a memorycontroller 1265 for access to SDRAM or SRAM memory devices. Someintegrated circuits additionally include an embedded security engine1270.

FIGS. 13A-13B are block diagrams illustrating exemplary graphicsprocessors for use within an SoC, according to embodiments describedherein. FIG. 13A illustrates an exemplary graphics processor 1310 of asystem on a chip integrated circuit that may be fabricated using one ormore IP cores, according to an embodiment. FIG. 13B illustrates anadditional exemplary graphics processor 1340 of a system on a chipintegrated circuit that may be fabricated using one or more IP cores,according to an embodiment. Graphics processor 1310 of FIG. 13A is anexample of a low power graphics processor core. Graphics processor 1340of FIG. 13B is an example of a higher performance graphics processorcore. Each of the graphics processors 1310, 1340 can be variants of thegraphics processor 1210 of FIG. 12.

As shown in FIG. 13A, graphics processor 1310 includes a vertexprocessor 1305 and one or more fragment processor(s) 1315A-1315N (e.g.,1315A, 1315B, 1315C, 1315D, through 1315N-1, and 1315N). Graphicsprocessor 1310 can execute different shader programs via separate logic,such that the vertex processor 1305 is optimized to execute operationsfor vertex shader programs, while the one or more fragment processor(s)1315A-1315N execute fragment (e.g., pixel) shading operations forfragment or pixel shader programs. The vertex processor 1305 performsthe vertex processing stage of the 3D graphics pipeline and generatesprimitives and vertex data. The fragment processor(s) 1315A-1315N usethe primitive and vertex data generated by the vertex processor 1305 toproduce a framebuffer that is displayed on a display device. In oneembodiment, the fragment processor(s) 1315A-1315N are optimized toexecute fragment shader programs as provided for in the OpenGL API,which may be used to perform similar operations as a pixel shaderprogram as provided for in the Direct 3D API.

Graphics processor 1310 additionally includes one or more memorymanagement units (MMUs) 1320A-1320B, cache(s) 1325A-1325B, and circuitinterconnect(s) 1330A-1330B. The one or more MMU(s) 1320A-1320B providefor virtual to physical address mapping for the graphics processor 1310,including for the vertex processor 1305 and/or fragment processor(s)1315A-1315N, which may reference vertex or image/texture data stored inmemory, in addition to vertex or image/texture data stored in the one ormore cache(s) 1325A-1325B. In one embodiment the one or more MMU(s)1320A-1320B may be synchronized with other MMUs within the system,including one or more MMUs associated with the one or more applicationprocessor(s) 1205, image processor 1215, and/or video processor 1220 ofFIG. 12, such that each processor 1205-1220 can participate in a sharedor unified virtual memory system. The one or more circuitinterconnect(s) 1330A-1330B enable graphics processor 1310 to interfacewith other IP cores within the SoC, either via an internal bus of theSoC or via a direct connection, according to embodiments.

As shown FIG. 13B, graphics processor 1340 includes the one or moreMMU(s) 1320A-1320B, cache(s) 1325A-1325B, and circuit interconnect(s)1330A-1330B of the graphics processor 1310 of FIG. 13A. Graphicsprocessor 1340 includes one or more shader core(s) 1355A-1355N (e.g.,1455A, 1355B, 1355C, 1355D, 1355E, 1355F, through 1355N-1, and 1355N),which provides for a unified shader core architecture in which a singlecore or type or core can execute all types of programmable shader code,including shader program code to implement vertex shaders, fragmentshaders, and/or compute shaders. The exact number of shader corespresent can vary among embodiments and implementations. Additionally,graphics processor 1340 includes an inter-core task manager 1345, whichacts as a thread dispatcher to dispatch execution threads to one or moreshader cores 1355A-1355N and a tiling unit 1358 to accelerate tilingoperations for tile-based rendering, in which rendering operations for ascene are subdivided in image space, for example to exploit localspatial coherence within a scene or to optimize use of internal caches.

Techniques for Enabling EarlyZ for Conservative Rasterization

As noted above, due to the incompatibility of EarlyZ and conservativerasterization, at present applications typically disable EarlyZ whenmaking use of conservative rasterization. As it is desirable to enableEarlyZ for various performance and efficiency reasons (e.g., reductionof the number of pixel shader threads launched, which has a directpositive impact on performance and memory bandwidth), embodimentsdescribed herein seek to facilitate use of conservative rasterizationwithout completely disabling EarlyZ functionality.

As the GPU already maintains inner coverage information, which trackspartially and fully covered pixels when conservative rasterization ison, the general idea in accordance with various embodiments describedherein is to expose that information to one or more units of theconservative rasterization pipeline. In this manner, at a minimum EarlyZcan be enabled for fully covered pixels. Additionally, the approach canbe extended to perform EarlyZ even for partially covered pixels by, forexample, clamping the extrapolated Z value to the minimum and maximum Zvalues of the primitive being rasterized.

According to some embodiments, a method for processing pixels by aconservative rasterization pipeline of a GPU involves a given pixelshader thread of the conservative rasterization pipeline concurrentlyprocessing both partially and fully covered pixels. A conservativerasterizer of the conservative rasterizer pipeline receives a primitiveto be rasterized. Based on multiple vertices of the primitive, theconservative rasterizer creates a pixel location stream and innercoverage data for each pixel within the pixel location stream. The innercoverage data is indicative of whether the corresponding pixel is fullycovered by the primitive or partially covered by the primitive. For eachbatch of pixels of the pixel location stream, the conservativerasterizer launches a thread of a pixel shader, including causing EarlyZto be performed for those pixels of the batch of pixels that are fullycovered by the primitive and causing EarlyZ not to be performed forthose pixels of the batch of pixels that are partially covered by theprimitive. For example, the conservative rasterizer may enable EarlyZfor blocks of fully covered pixels and disable EarlyZ for blocks ofpartially covered pixels, thereby bypassing EarlyZ processing forpartially covered pixels. Alternatively, the same result may be achievedby exposing the inner coverage data to the EarlyZ unit and configuringthe EarlyZ unit to simply pass through the partially covered pixelswithout performing depth processing. For its part, the pixel shaderproduces a stream of pixel updates by conditionally processing thosepixels remaining in the pixel location stream to incorporate pixelshading characteristics, including, for those pixels of the pixellocation stream that are partially covered by the primitive, computing adepth value for the pixels and causing LateZ to be performed for thosepixels.

In other embodiments, the conservative rasterizer may launch separatethreads of the pixel shader for blocks of partially covered pixels andfor blocks of fully covered pixels. Since, a given block of pixelsprocessed by the pixel shader will be either all partially covered orall fully covered pixels, the pixel shader can avoid conditionalprocessing of individual pixels and can instead process the entire blockof pixels in accordance with the inner coverage data specified as thepixel block level indicating whether the block at issue contains pixelsthat are fully or partially covered by the primitive being rasterized.As above, the conservative rasterizer receives a primitive to berasterized and creates, based on multiple vertices of the primitive, apixel location stream and inner coverage data for each pixel within thepixel location stream indicative of whether the corresponding pixel isfully covered by the primitive or partially covered by the primitive.The conservative rasterizer then groups the pixels of the pixel locationstream into two separate groups—a first group including those of thepixels that are fully covered by the primitive and a second groupincluding those pixels that are partially covered by the primitive. Theconservative rasterizer launches a first thread of the pixel shader fora batch or block of pixels from the first group, including causingEarlyZ to be performed for all pixels in the block/batch. Theconservative rasterizer launches a second thread of the pixel shader fora batch or block of pixels from the second group, including causingperformance of EarlyZ to be skipped for all pixels in the batch. Thefirst thread of the pixel shader generates a first stream of pixelupdates that incorporates pixel shading characteristics and causes LateZto be skipped for all pixels in the batch/block at issue (as they areall known to be fully covered pixels). The second thread of the pixelshader generates a second stream of pixel updates that incorporatespixel shading characteristics, including computing a depth value for thepixels and causing LateZ to be performed for all pixels in thebatch/block at issue (as they are all known to be partially coveredpixels).

In alternative embodiments, the conservative rasterizer may enableEarlyZ for both partially and fully covered pixels, relying on improvedcapabilities of the EarlyZ unit to clamp extrapolated depth values tothe minimum and maximum values of the primitive being rasterized. Asabove, the conservative rasterizer receives a primitive to be rasterizedand creates, based on multiple vertices of the primitive, a pixellocation stream and inner coverage data for each pixel within the pixellocation stream indicative of whether the corresponding pixel is fullycovered by the primitive or partially covered by the primitive. Theconservative rasterizer causes EarlyZ to be performed for blocks/batchesof pixels potentially including both partially and fully covered pixels.Based on the inner coverage data, the EarlyZ unit conditionallyprocesses the pixels, including extrapolating and clamping depth valuesfor partially covered pixels. For partially covered pixels EarlyZoptimization processing is performed based on the clamped depth valuesand for fully covered pixels EarlyZ optimization processing is performedbased on existing depth values. In such an embodiment, pixel shaderthreads can be performed without reference to the inner coverage data asno further conditional processing or LateZ processing is required.

High-Level View of the Graphics Pipeline

FIG. 15 is a block diagram illustrating a high-level architectural viewof distribution of graphics pipeline functionality between a centralprocessing unit (CPU) 1510 and a graphics processing unit (GPU) 1520according to an embodiment. In the context of the present example, thegraphics pipeline is divided into four parts, application 1511, geometry1522, rasterization 1524 and an output merger stage 1526. Theapplication 1511 is typically executed by software on the CPU 1510,including initiating changes to the scene depicted on a display device(not shown) based on, for example, user interaction via an input deviceor during an animation process. Graphics APIs (e.g., Direct3D andOpenGL) abstract the underlying hardware implementation of a givengraphics hardware accelerator, for example, to, among other things,provide software programmers with a uniform interface. Non-limitingexamples of tasks that are typically performed in the application 1511,include collision detection, animation, and morphing.

The geometry stage 1522, the rasterization stage 1524 and the outputmerger stage 1526 are typically performed by the GPU 1520. The GPU 1520may be integrated within the CPU 1510 or a discrete device coupled tothe CPU 1510 via an interface technology, such as PCI Express (PCIe) orthe like. The geometry stage 1522 is generally responsible foroperations associated with continuous primitives (e.g., polygons) andtheir vertices. The rasterization stage 1524 involves, among otherthings, the creation of discrete fragments from the continuousprimitives, determining the visibility of pixels, for example, in thecase of overlapping primitives and computing color and other attributesof pixels. Earlier identification of an occluded pixel by way of EarlyZ,for example, allows fewer resources and processing to be invested on apixel that will not ultimately be displayed. The output merger stage1526 generally involves generation of the final rendered pixel colorusing, a combination of, among other things, pipeline state and thepixel data generated by the pixel shaders. As FIG. 15 is intendedprimarily to provide context for the rasterization stage 1524, for sakeof brevity, the other stages have been summarized at a high-level.Non-limiting examples of potential realization and operation of aconservative rasterization pipeline implemented within the rasterizationstage 1524 will now be discussed with reference to FIGS. 16-20.

A First Embodiment of a Conservative Rasterization Pipeline

FIG. 16 is a block diagram illustrating interactions among components ofa conservative rasterization pipeline 1600 according to a firstembodiment. In one embodiment, conservative rasterization pipeline 1600represents a subset of functionality implemented within rasterizationstage 1524 of FIG. 15. In the context of the present example, theconservative rasterization pipeline 1600 includes a conservativerasterizer 1610, an EarlyZ unit 1620, a pixel shader 1630, and a LateZunit 1640. The input to the conservative rasterizer 1610 is generallyreferred to herein as a primitive stream 1601, representing continuousprimitives output by a previous graphics pipeline stage (e.g., geometrystage 1522) that are to be rasterized. The output of the conservativerasterizer 1610 and the input to the pixel shader 1630 is generallyreferred to herein as a pixel location stream 1615, which includes,among other data, the coordinates/locations of the pixels that are to beshaded. While only one pixel shader 1630 is shown in this example forthe sake of simplicity, those skilled in the art will appreciate thepixel location stream 1615 may be distributed among numerous pixelshaders. The output of the pixel shader 1630 is generally referred toherein as pixel updates 1635, a linear sequential stream of pixel datathat includes pixel shading characteristics/traits (e.g., color, z-depthand alpha value) for each pixel.

In general, in the context of the present example, EarlyZ optimizationprocessing is performed for some pixels (fully covered pixels) for whichLateZ pixel rejection processing is skipped and EarlyZ optimizationprocessing is skipped for other pixels (partially covered pixels) forwhich LateZ pixel rejection processing is performed. As those skilled inthe art will appreciate and as described further below, the EarlyZ unit1620 and/or the LateZ unit 1640 can be bypassed by the previous stage(i.e., the conservative rasterizer 1610 and the pixel shader 1630,respectively) or the pixels for which processing by the EarlyZ unit 1620and/or the LateZ unit 1640 are to be skipped can be provided to the unitat issue and simply passed through based on inner coverage data 1623generated by the conservative rasterizer 1610.

In one embodiment, the conservative rasterizer 1610 generates the pixellocation stream 1615 based on the vertices of a continuous primitivereceived from the primitive stream 1601. There are two types of pixelsof interest, those that are fully covered by the primitive beingrasterized and those that are partially covered. In one embodiment, theconservative rasterizer 1610 creates inner coverage data 1623 to trackthese two types of pixels. As can be seen in FIG. 16, the inner coveragedata 1623 may also be exposed to and used by one or more of the EarlyZunit 1620, the pixel shader 1630, and the LateZ unit 1640 depending uponthe particular implementation as described further below.

In the context of the present example, fully covered pixels 1611 gothrough EarlyZ optimization processing while LateZ optimizationprocessing is applied downstream to partially covered pixels 1632 afterthey are output from the pixel shader 1630. In one embodiment, theconservative rasterizer 1610 causes EarlyZ optimization processing to beperformed for the fully covered pixels 1611 and causes EarlyZoptimization processing not to be performed for the partially coveredpixels 1612. For example, in one embodiment, the conservative rasterizer1610 enables EarlyZ for a block of fully covered pixels 1611 as thoughconservative rasterization is off. Depending upon the particularimplementation, the block may include 4, 8, 16 or 32 pixels. Withrespect to the partially covered pixels 1612, in one embodiment,conditional processing may be performed internal to the conservativerasterizer 1610 (e.g., by disabling the EarlyZ test for a particularblock of partially covered pixels 1612) or internal to the EarlyZ unit1620 (e.g., treating the partially covered pixels 1612 identified by theinner coverage data 1623 as pass through values). In the latter case,the EarlyZ unit 1620 may use the inner coverage mask to mask out theEarlyZ operation for partially covered pixels.

In the context of the present example, a pixel shader thread may operateon a block of pixels including both partially covered and fully coveredpixels. As such, the pixel shader 1630 conditionally processes theindividual pixels of the pixel location stream 1615 based on the innercoverage data. For example, the pixel shader 1630 processing the pixellocation stream to incorporate pixel shading characteristics for bothfully covered and partially covered pixels, but may only compute depthvalues for the partially covered pixels 1612. Further, the pixel shader1630 may cause partially covered pixels 1632 within the pixel updates1635 to be processed by the LateZ unit 1640, whereas fully coveredpixels 1631 within the pixel updates 1635 bypass the LateZ unit 1640.Alternatively, in one embodiment, all pixels within the pixel updates1635 can be directed through the LateZ unit 1640, with the LateZ unitdifferentially treating the fully covered pixels 1631 (e.g., treatingthe fully covered pixels 1631 identified by the inner coverage data 1623as pass through values) and the partially covered pixels 1632 (e.g.,performing LateZ pixel rejection processing).

FIG. 17 is a flow diagram illustrating conservative rasterizationpipeline processing according to the first embodiment. At block 1710,the conservative rasterizer (e.g., conservative rasterizer 1610)receives a primitive to be rasterized. For example, the conservativerasterizer may process one primitive at a time from the primitive stream1601.

At block 1720, assuming for sake of illustration the primitive is to besolid filled, the conservative rasterizer creates a pixel locationstream (e.g., pixel location stream 1615) corresponding to those pixelstouched by the primitive as well as those pixels that are fullyencompassed by the primitive. As the conservative rasterizer creates thepixel location stream it also generates inner coverage data 1623. Forexample, the conservative rasterizer may project the vertices of theprimitive onto the screen and then determine whether a given discretefragment (pixel) meets the requisite conditions with respect to theresulting two-dimensional polygon (e.g., the 2D triangle 1410 depictedin FIG. 14B).

In an embodiment, the inner coverage data 1623 may be represented in theform of a matrix corresponding to the pixel locations. In embodiments inwhich an inner coverage status indication (e.g., a bit flag) is trackedat a per-pixel level (e.g., 0=the corresponding pixel is fully coveredby the primitive; 1=the corresponding pixel is partially covered by theprimitive) for a block of pixels, the inner coverage data 1623 may alsobe referred to herein as an inner coverage mask.

At decision block 1730, it is determined whether a pixel at issue isfully covered. If so, processing continues with decision block 1740;otherwise processing branches to decision block 1760. As noted above,this determination may be performed with reference to the inner coveragedata 1623 and depending upon the particular implementation may beperformed internal to the conservative rasterizer or internal to theEarlyZ unit (e.g., EarlyZ unit 1620).

At decision block 1740, EarlyZ optimization processing is performed bythe EarlyZ unit and a decision regarding to keep or reject the pixel atissue is made. For example, the EarlyZ unit may perform an early depthtest on the Z-value of the pixel at issue to identify whether the pixelwill fail the depth text (i.e., is occluded) and therefore need not berun through the pixel shader. If the pixel fails the early depth test,the processing branches to block 1750; otherwise, processing continueswith block 1760.

At block 1750, the pixel has determined to be occluded and is thereforeremoved from the pixel location stream as there is no need to performany further processing on the pixel.

According to one embodiment, as a block of pixels is available to beprocessed by a pixel shader, a pixel shader thread is launched andprocessing continues with block 1760. As those skilled in the art willappreciate, since EarlyZ optimization may drop some pixels from thepixel location stream 1615, more than one block of pixels may have toundergo EarlyZ optimization processing to produce an output block ofpixels from the EarlyZ unit. As such, in one embodiment, a pixel shaderthread may be launched with a heterogeneous block of pixels including amix of fully covered pixels and partially covered pixels.

At block 1760, the pixel shader (e.g., pixel shader 1630) incorporatespixel shading characteristics (excluding z-depth) into the pixellocation stream 1615. Then, processing continues with decision block1770.

In the context of the present example, because the block of pixels beingprocessed by the pixel shader may include both fully covered andpartially covered pixels and depth values have been previouslycalculated for the fully covered pixels, the pixel shader treats thepixels differentially based on the inner coverage data 1623.

At decision block 1770, the pixel shader determines on a pixel-by-pixelbasis, with reference to the inner coverage data 1623, whether the pixelat issue is fully covered. When the pixel is fully covered, processingbranches to block 1780; otherwise pixel shading and conservativerasterizer pipeline processing for the pixel is complete.

At block 1780, depth values are computed for partially covered pixelsand this information is added to the pixel updates 1635.

At block 1790, LateZ pixel rejection is performed on the partiallycovered pixels based on the depth values calculated in block 1780 asdepth testing has yet to be performed for these pixels. At this point,conservative rasterizer pipeline processing is complete.

A Second Embodiment of a Conservative Rasterization Pipeline

FIG. 18 is a block diagram illustrating interactions among components ofa conservative rasterization pipeline 1800 according to a secondembodiment. In one embodiment, conservative rasterization pipeline 1800represents a subset of functionality implemented within rasterizationstage 1524 of FIG. 15. In the context of the present example, theconservative rasterization pipeline 1800 includes a conservativerasterizer 1810, an EarlyZ unit 1820, a buffer 1825, two different pixelshader threads 1830 a-b, and a LateZ unit 1840. As above, the input tothe conservative rasterizer 1810 is in the form of a primitive stream1601, the output of the conservative rasterizer 1810 and the input tothe pixel shader threads 1830 a-b is generally referred to as a pixellocation stream 1615, and the output of the pixel shader threads 1630a-b is in the form of pixel updates 1635.

In general, in the context of the present example and similar to thefirst embodiment, EarlyZ optimization processing is performed on fullycovered pixels for which LateZ pixel rejection processing is skipped andEarlyZ optimization processing is skipped for partially covered pixelson which LateZ pixel rejection processing is performed; however, thisapproach may be suitable for GPU architectures that may be limited toperforming EarlyZ at the level of granularity of a block of pixels. Theoutput of the pixel shader 1630 is generally referred to herein as pixelupdates 1635, a linear sequential stream of pixel data that includespixel shading characteristics/traits (e.g., color, z-depth and alphavalue) for each pixel. While two pixel shader treads 1830 a-b are shownin this example for the sake of efficiently illustrating separateprocessing of fully covered pixels and partially covered pixels, thoseskilled in the art will appreciate the pixel location stream 1615 may bedistributed among numerous additional pixel shader threads.

In one embodiment, the conservative rasterizer 1810 generates the pixellocation stream 1615 based on the vertices of a continuous primitivereceived from the primitive stream 1601 and creates inner coverage data1823 to track whether pixels (or blocks of pixels) are fully orpartially covered by the primitive. In some embodiments, inner coveragedata 1823 may include per-pixel granularity status indications for useby the conservative rasterizer 1810; however such status indications maybe tracked at the pixel block level of granularity subsequent to theconservative rasterizer 1810 for use by the pixel shader threads 1830a-b as the pixel shader threads 1830 a-b operate on homogeneous blocksof pixels and each pixel shader thread can therefore simply be informedat a pixel block level whether the block it is processing is comprisedof fully covered or partially covered pixels.

In the context of the present example, fully covered pixels 1811 gothrough EarlyZ optimization processing while LateZ optimizationprocessing is applied downstream to partially covered pixels 1832 afterthey are output from pixel shader thread 1830 b. In one embodiment, theconservative rasterizer 1810 conditionally processes the pixels,separately grouping blocks of fully covered pixels 1811 and blocks ofpartially covered pixels 1812. Blocks of fully covered pixels 1811 aresubmitted to the EarlyZ unit 1820 and are processed by pixel shaderthread 1830 a. In parallel, as blocks of partially covered pixels 1812have been accumulated within buffer 1825, they are processed by pixelshader thread 1830 b. According to one embodiment, the conservativerasterizer 1810 launches pixel shader thread 1830 a for fully coveredpixels as though conservative rasterization is off with EarlyZ enabledand launches pixel shader thread 1830 b separately for partially coveredpixels with EarlyZ disabled.

As should be appreciated, one difference between this example and thatillustrated by FIG. 16 is the pixel shader threads 1830 a-b processhomogeneous blocks of fully covered pixels and partially covered pixels,respectively. As such, a pixel shader can avoid conditional processingon a per-pixel basis and can simply be informed at a block level (e.g.,via the inner coverage data 1823) whether the block of pixels it iscurrently processing contains fully covered pixels or partially coveredpixels.

According to one embodiment, pixel shader thread 1830 a computes pixelshading characteristics/traits (other than z-depth, which has alreadybeen performed by the EarlyZ unit 1820) for each pixel of the block ofpixels to produce fully covered pixels 1831 of the pixel updates 1635.For its part, pixel shader thread 1830 b computes pixel shadingcharacteristics/traits (including z-depth on which LateZ willsubsequently be performed) for each pixel of the block of pixels toproduce partially covered pixels 1832 of the pixel updates 1635.

FIG. 19 is a flow diagram illustrating conservative rasterizationpipeline processing according to the second embodiment. At block 1910,the conservative rasterizer (e.g., conservative rasterizer 1810)receives a primitive to be rasterized. For example, the conservativerasterizer may process one primitive at a time from the primitive stream1601.

At block 1920, assuming for sake of illustration the primitive is to besolid filled, the conservative rasterizer creates a pixel locationstream (e.g., pixel location stream 1615) corresponding to those pixelstouched by the primitive as well as those pixels fully encompassed bythe primitive. As the conservative rasterizer creates the pixel locationstream it also generates inner coverage data 1823. For example, theconservative rasterizer may project the vertices of the primitive ontothe screen and then determine whether a given discrete fragment (pixel)meets the requisite conditions with respect to the resultingtwo-dimensional polygon (e.g., the 2D triangle 1410 depicted in FIG.14B).

In one embodiment, during processing by the conservative rasterizer, theinner coverage data 1823 may be represented in the form of a matrix ormask corresponding to the pixel locations and may include statusindications (e.g., bit flags) at a per-pixel level (e.g., 0=thecorresponding pixel is fully covered by the primitive; 1=thecorresponding pixel is partially covered by the primitive) for a blockof pixels. Because pixel shader threads (e.g., pixel shader threads 1830a-b) process homogeneous blocks of either fully covered or partiallycovered pixels, after the conservative rasterizer, the inner coveragedata 1823 may simply track the status indications at a block-level ofgranularity. As there may be two different forms of inner coverage dataat particular times during conservative rasterization pipeline in thisexample, the first form (having per-pixel status indications) may bereferred to as a first set of inner coverage data and the second form(having block-level status indications) may be referred to as a secondset of inner coverage data.

At decision block 1930, the conservative rasterizer determines whether apixel at issue is fully covered with reference to the inner coveragedata 1823, for example. If so, processing continues with block 1970;otherwise processing branches to block 1940. As the conservativerasterizer divides the pixel location stream 1615 into two separategroups including blocks of fully covered pixels and blocks of partiallycovered pixels, it may also create the second set of inner coveragedata.

At block 1970, the EarlyZ unit (e.g., EarlyZ unit 1820) performs EarlyZoptimization processing on a block of fully covered pixels of the pixellocation stream 1615 output by the conservative rasterizer. As blocks offully covered pixels are available for the next stage, processingcontinues with block 1980.

At block 1980, a pixel shader thread (e.g., pixel shader thread 1830 a)is launched for a homogeneous block of fully covered pixels and based onthe inner coverage data the pixel shader thread incorporates appropriatepixel shading characteristics/traits (excluding performing depth valuecalculation) for each pixel to produce a portion of pixel updates 1635.At this point, conservative rasterizer pipeline processing is completefor this block of pixels.

At block 1940, partially covered pixels of the pixel location stream1615 output by the conservative rasterizer are buffered (e.g., in buffer1820) until a block of partially covered pixels are available for thenext stage.

At block 1950, a pixel shader thread (e.g., pixel shader thread 1830 b)is launched for a homogeneous block of partially covered pixels andbased on the inner coverage data the pixel shader thread incorporatesappropriate pixel shading characteristics/traits (including depthvalues) for each pixel to produce a portion of pixel updates 1635, whichare put through LateZ processing at block 1960.

At block 1960, LateZ pixel rejection is performed on the block ofpartially covered pixels based on the depth values calculated in block1780 as depth testing has yet to be performed for this block of pixels.At this point, conservative rasterizer pipeline processing is completefor this block of pixels.

A Third Embodiment of a Conservative Rasterization Pipeline

FIG. 20 is a block diagram illustrating interactions among components ofa conservative rasterization pipeline 2000 according to a thirdembodiment. In one embodiment, conservative rasterization pipeline 2000represents a subset of functionality implemented within rasterizationstage 1524 of FIG. 15. In the context of the present example, theconservative rasterization pipeline 2000 includes a conservativerasterizer 2010, an EarlyZ unit 2020, and a pixel shader 2030. As above,the input to the conservative rasterizer 2010 is in the form of aprimitive stream 1601, the output of the conservative rasterizer 2010and the input to the pixel shader 2030 is generally referred to as apixel location stream 1615, and the output of the pixel shader 2030 isin the form of pixel updates 1635. Again, while only one pixel shader2030 is shown in this example for the sake of simplicity, those skilledin the art will appreciate the pixel location stream 1615 may bedistributed among numerous pixel shaders.

In general, in the context of the present example, as a result ofimprovements made to the EarlyZ unit 2020, EarlyZ optimizationprocessing is performed on both fully covered pixels 2011 and partiallycovered pixels 2012 of the pixel location stream 1615. As such, there isno need for LateZ pixel rejection processing following the pixel shader2030.

In one embodiment, the conservative rasterizer 2010 generates the pixellocation stream 1615 based on the vertices of a continuous primitivereceived from the primitive stream 1601 and creates inner coverage data1823 to track whether pixels (or blocks of pixels) are fully orpartially covered by the primitive. Depending upon the particularimplementation, for example, whether fully covered pixels and partiallycovered pixels are submitted to the EarlyZ unit 2020 in the form of ahomogeneous block of pixels (i.e., a block comprised entirely of fullycovered pixels or entirely of partially covered pixels) or aheterogeneous block of pixels (i.e., a block that may include both fullycovered and partially covered pixels), inner coverage data 1823 mayinclude per-pixel granularity status indications and/or such statusindications may be tracked at the pixel block level of granularity.

In the context of the present example, the EarlyZ unit 2020 adds thecapability to at least clamp extrapolated depth values for partiallycovered pixels to the minimum and maximum of the primitive beingrasterized so as to allow EarlyZ optimization processing to be enabledfor both fully covered pixels 2011 and partially covered pixels. 2012.In one embodiment, selective clamping based on inner coverage data canbe avoided by clamping all depth values (e.g., extrapolated depth valuesfor partially covered pixels and depth values for fully covered pixels)calculated by the EarlyZ unit 2020 to the minimum and maximum of theprimitive being rasterized. As such, those skilled in the art willappreciate that while the inner coverage data 1823 is shown in FIG. 20as a potential input to the EarlyZ unit 2020, in some embodiments, theEarlyZ unit 2020 does not make use of the inner coverage data 1823 andtherefore it need not be exposed in such embodiments.

In the context of the present example, since depth testing haspreviously been performed on all pixels prior to receipt by the pixelshader 2030, during computation of pixel shading characteristics/trainsfor the pixels being processed, the pixel shader 2030 need not computez-depth values for the pixels. Similarly, there is no need for LateZprocessing on the pixel updates 1635 output from the pixel shader 2030.

Many of the methods are described in their most basic form, butprocesses can be added to or deleted from any of the methods andinformation can be added or subtracted from any of the describedmessages without departing from the basic scope of the presentembodiments. It will be apparent to those skilled in the art that manyfurther modifications and adaptations can be made. The particularembodiments are not provided to limit the concept but to illustrate it.The scope of the embodiments is not to be determined by the specificexamples provided above but only by the claims below.

If it is said that an element “A” is coupled to or with element “B,”element A may be directly coupled to element B or be indirectly coupledthrough, for example, element C. When the specification or claims statethat a component, feature, structure, process, or characteristic A“causes” a component, feature, structure, process, or characteristic B,it means that “A” is at least a partial cause of “B” but that there mayalso be at least one other component, feature, structure, process, orcharacteristic that assists in causing “B.” If the specificationindicates that a component, feature, structure, process, orcharacteristic “may”, “might”, or “could” be included, that particularcomponent, feature, structure, process, or characteristic is notrequired to be included. If the specification or claim refers to “a” or“an” element, this does not mean there is only one of the describedelements.

An embodiment is an implementation or example. Reference in thespecification to “an embodiment,” “one embodiment,” “some embodiments,”or “other embodiments” means that a particular feature, structure, orcharacteristic described in connection with the embodiments is includedin at least some embodiments, but not necessarily all embodiments. Thevarious appearances of “an embodiment,” “one embodiment,” or “someembodiments” are not necessarily all referring to the same embodiments.It should be appreciated that in the foregoing description of exemplaryembodiments, various features are sometimes grouped together in a singleembodiment, figure, or description thereof for the purpose ofstreamlining the disclosure and aiding in the understanding of one ormore of the various novel aspects. This method of disclosure, however,is not to be interpreted as reflecting an intention that the claimedembodiments requires more features than are expressly recited in eachclaim. Rather, as the following claims reflect, novel aspects lie inless than all features of a single foregoing disclosed embodiment. Thus,the claims are hereby expressly incorporated into this description, witheach claim standing on its own as a separate embodiment.

The following clauses and/or examples pertain to further embodiments orexamples. Specifics in the examples may be used anywhere in one or moreembodiments. The various features of the different embodiments orexamples may be variously combined with some features included andothers excluded to suit a variety of different applications. Examplesmay include subject matter such as a method, means for performing actsof the method, at least one machine-readable medium includinginstructions that, when performed by a machine cause the machine toperform acts of the method, or of an apparatus or system forfacilitating hybrid communication according to embodiments and examplesdescribed herein.

Some embodiments pertain to Example 1 that includes a graphicsprocessing unit (GPU) supporting EarlyZ for conservative rasterization,the GPU comprising: a conservative rasterizer operable to: process aprimitive stream and generate (i) a pixel location stream based onvertices of a primitive from the primitive stream and (ii) innercoverage data for each pixel within the pixel location stream, whereinthe inner coverage data indicates for a given pixel within the pixellocation stream whether the given pixel is fully covered by a primitivewith which it is associated or partially covered by the primitive; andlaunch pixel shader processing for blocks of pixels of the pixellocation stream, including causing early depth testing to be performedfor those pixels of the blocks of pixels that are fully covered by theprimitive and causing early depth testing to be performed for thosepixels of the blocks of pixels that are partially covered by theprimitive; an EarlyZ unit operable to perform the early depth testing todiscard occluded pixels from the pixel location stream prior to pixelshading; and a plurality of pixel shaders operable to perform the pixelshader processing to generate pixel updates by conditionally processingthe pixel location stream and incorporating pixel shadingcharacteristics into the pixel updates, including for those pixels ofthe pixel location stream that are partially covered by the primitivecomputing a depth value for the pixels and causing late depth testing tobe performed for the pixels; and a LateZ unit operable to perform thelate depth testing to discard occluded pixels from the pixel updates.

Example 2 includes the subject matter of Example 1, wherein theconservative rasterizer causes early depth testing to be performed byenabling the EarlyZ unit for those pixels of the block of pixels thatare fully covered by the primitive.

Example 3 includes the subject matter of Examples 1-2, wherein theconservative rasterizer causes early depth testing not to be performedby disabling the EarlyZ unit for those pixels of the block of pixelsthat are partially covered by the primitive.

Example 4 includes the subject matter of Examples 1-3, wherein theEarlyZ unit is operable to use the inner coverage data to mask out theearly depth testing for partially covered pixels.

Some embodiments pertain to Example 5 that includes a method forprocessing pixels by a conservative rasterization pipeline, the methodcomprising: receiving, by a conservative rasterizer of a conservativerasterizer pipeline of a graphics processing unit, a primitive to berasterized; creating, by the conservative rasterizer, based on aplurality of vertices of the primitive, a pixel location stream andinner coverage data for each pixel within the pixel location stream,wherein the inner coverage data is indicative of whether thecorresponding pixel is fully covered by the primitive or partiallycovered by the primitive; for each block of pixels of the pixel locationstream, launching, by the conservative rasterizer, a thread of a pixelshader of the conservative rasterizer pipeline, including causing EarlyZto be performed for those pixels of the block of pixels that are fullycovered by the primitive and causing EarlyZ not to be performed forthose pixels of the block of pixels that are partially covered by theprimitive; and generating, by the pixel shader, a stream of pixelupdates by conditionally processing the pixel location stream toincorporate pixel shading characteristics, including for those pixels ofthe pixel location stream that are partially covered by the primitivecomputing a depth value for the pixels and causing LateZ to be performedfor the pixels.

Example 6 includes the subject matter of Example 5, wherein said causingEarlyZ to be performed comprises enabling EarlyZ for those pixels of theblock of pixels that are fully covered by the primitive.

Example 7 includes the subject matter of Examples 5-6, wherein saidcausing EarlyZ not to be performed comprises bypassing EarlyZ for thosepixels of the block of pixels that are partially covered by theprimitive.

Example 8 includes the subject matter of Examples 5-7, wherein saidcausing EarlyZ not to be performed comprises disabling EarlyZ for thosepixels of the block of pixels that are partially covered by theprimitive.

Example 9 includes the subject matter of Examples 5-8, wherein saidcausing EarlyZ not to be performed comprises causing an EarlyZ unit toconditionally process pixels of the pixel location stream based on theinner coverage data including passing through unchanged those pixels ofthe block of pixels that are partially covered by the primitive.

Some embodiments pertain to Example 10 that includes a graphicsprocessing unit (GPU) supporting EarlyZ for conservative rasterization,the GPU comprising: a conservative rasterizer operable to: process aprimitive stream and generate (i) a pixel location stream based onvertices of a primitive from the primitive stream and (ii) a first setof inner coverage data for each pixel within the pixel location stream,wherein the first set of inner coverage data indicates for a given pixelwithin the pixel location stream whether the given pixel is fullycovered by a primitive with which it is associated or partially coveredby the primitive; group pixels of the pixel location stream into a firstgroup and a second group, based on the first set of inner coverage data,wherein the first group includes those of the pixels that are fullycovered by the primitive and the second group includes those pixels thatare partially covered by the primitive; and launch separate pixel shaderthreads, including a first thread for a first block of pixels of thefirst group and second thread for a second block of pixels of the secondgroup; a first pixel shader operable to perform the first thread; and asecond pixel shader operable to perform the second thread.

Example 11 includes the subject matter of Example 10, further comprisingan EarlyZ unit operable to perform early depth testing and wherein theconservative rasterizer is further operable to: create a second set ofinner coverage data indicating at a pixel-block level (i) all pixels inthe first block are fully covered by the primitive and (ii) all pixelsin the second block are partially covered by the primitive; and causethe early depth testing to be performed for pixels in the first blockand to cause the early depth testing not to be performed for pixels inthe second block.

Example 12 includes the subject matter of Examples 10-11, furthercomprising a LateZ unit operable to perform late depth testing andwherein: based on the second set of inner coverage data, the first pixelshader is further operable to generate a first stream of pixel updatesthat incorporates pixel shading characteristics and cause the late depthtesting to be skipped for all pixels in the first block; and based onthe second set of inner coverage data, the second pixel shader isfurther operable to generate a second stream of pixel updates thatincorporates pixel shading characteristics, compute a depth value forall pixels in the second block, and cause the late depth testing to beperformed for all pixels in the second block.

Some embodiments pertain to Example 13 that includes a method forprocessing pixels by a conservative rasterization pipeline, the methodcomprising: receiving, by a conservative rasterizer of a conservativerasterizer pipeline of a graphics processing unit, a primitive to berasterized; creating, by the conservative rasterizer, based on aplurality of vertices of the primitive, a pixel location stream and afirst set of inner coverage data for each pixel within the pixellocation stream, wherein first set of the inner coverage data isindicative of whether the corresponding pixel is fully covered by theprimitive or partially covered by the primitive; grouping, by theconservative rasterizer, based on the first set of inner coverage datapixels of the pixel location stream into a first group and a secondgroup, wherein the first group includes those of the pixels that arefully covered by the primitive and the second group includes thosepixels that are partially covered by the primitive; and launching, bythe conservative rasterizer, separate pixel shader threads for blocks ofpixels of the first group and blocks of pixels of the second group.

Example 14 includes the subject matter of Example 13, further comprisingcreating, by the conservative rasterizer, a second set of inner coveragedata indicating at a pixel-block level (i) all pixels in the first blockare fully covered by the primitive and (ii) all pixels in the secondblock are partially covered by the primitive.

Example 15 includes the subject matter of Examples 13-14, wherein saidlaunching, by the conservative rasterizer, separate pixel shader threadscomprises: for a first block of pixels of the first group, launching, bythe conservative rasterizer, a first thread of a pixel shader of theconservative rasterizer pipeline, including causing EarlyZ to beperformed for all pixels in the first block; and for a second block ofpixels of the second group, launching, by the conservative rasterizer, asecond thread of the pixel shader and causing performance of EarlyZ tobe skipped for all pixels in the second block.

Example 16 includes the subject matter of Examples 13-15, wherein saidcausing EarlyZ to be performed for all pixels in the first blockcomprises enabling EarlyZ for the first block.

Example 17 includes the subject matter of Examples 13-16, wherein saidcausing performance of EarlyZ to be skipped for all pixels in the secondblock comprises disabling EarlyZ for the second block.

Example 18 includes the subject matter of Examples 13-17, wherein saidlaunching, by the conservative rasterizer, separate pixel shader threadsfurther comprises: generating, by the first thread of the pixel shader,a first stream of pixel updates that incorporates pixel shadingcharacteristics, including causing LateZ to be skipped for the firstblock; and generating, by the second thread of the pixel shader, asecond stream of pixel updates that incorporates pixel shadingcharacteristics, including computing a depth value for all pixels in thesecond block and causing LateZ to be performed for all pixels in thesecond block.

Example 19 includes the subject matter of Examples 13-18, wherein saidcausing LateZ to be skipped for the first block comprises outputting thefirst block to a stage subsequent to a LateZ unit of the conservativerasterizer pipeline based on the second set of inner coverage data.

Example 20 includes the subject matter of Examples 13-19, wherein saidcausing LateZ to be performed for all pixels in the second blockcomprises outputting the second block to a LateZ unit of theconservative rasterizer pipeline based on the second set of innercoverage data.

Some embodiments pertain to Example 21 that includes one or morenon-transitory computer-readable storage mediums having stored thereonexecutable computer program instructions that, when executed by one ormore processors, cause the one or more processors to perform operationsincluding: receiving a primitive to be rasterized; creating based on aplurality of vertices of the primitive, a pixel location stream andinner coverage data for each pixel within the pixel location stream,wherein the inner coverage data is indicative of whether thecorresponding pixel is fully covered by the primitive or partiallycovered by the primitive; for each block of pixels of the pixel locationstream, launching a pixel shader process, including causing EarlyZ to beperformed for those pixels of the block of pixels that are fully coveredby the primitive and causing EarlyZ not to be performed for those pixelsof the block of pixels that are partially covered by the primitive; andgenerating, by the pixel shader process, a stream of pixel updates byconditionally processing the pixel location stream to incorporate pixelshading characteristics, including for those pixels of the pixellocation stream that are partially covered by the primitive computing adepth value for the pixels and causing LateZ to be performed for thepixels.

Example 22 includes the subject matter of Example 21, wherein saidcausing EarlyZ to be performed comprises enabling EarlyZ for thosepixels of the block of pixels that are fully covered by the primitive.

Example 23 includes the subject matter of Examples 21-22, wherein saidcausing EarlyZ not to be performed comprises bypassing EarlyZ for thosepixels of the block of pixels that are partially covered by theprimitive.

Example 24 includes the subject matter of Examples 21-23, wherein saidcausing EarlyZ not to be performed comprises disabling EarlyZ for thosepixels of the block of pixels that are partially covered by theprimitive.

Example 25 includes the subject matter of Examples 21-24, wherein saidcausing EarlyZ not to be performed comprises causing an EarlyZ unit toconditionally process pixels of the pixel location stream based on theinner coverage data including passing through unchanged those pixels ofthe block of pixels that are partially covered by the primitive.

Some embodiments pertain to Example 26 that includes a systemcomprising: a means for receiving a primitive to be rasterized; a meansfor creating based on a plurality of vertices of the primitive, a pixellocation stream and a first set of inner coverage data for each pixelwithin the pixel location stream, wherein first set of the innercoverage data is indicative of whether the corresponding pixel is fullycovered by the primitive or partially covered by the primitive; a meansfor grouping based on the first set of inner coverage data pixels of thepixel location stream into a first group and a second group, wherein thefirst group includes those of the pixels that are fully covered by theprimitive and the second group includes those pixels that are partiallycovered by the primitive; and a means for launching separate pixelshader threads for blocks of pixels of the first group and blocks ofpixels of the second group.

Example 27 includes the subject matter of Example 26, further comprisinga means for creating a second set of inner coverage data indicating at apixel-block level (i) all pixels in the first block are fully covered bythe primitive and (ii) all pixels in the second block are partiallycovered by the primitive.

Example 28 includes the subject matter of Examples 26-27, furthercomprising a means for launching for a first block of pixels of thefirst group a first thread of a pixel shader of the conservativerasterizer pipeline and for causing EarlyZ to be performed for allpixels in the first block; and a means for launching for a second blockof pixels of the second group a second thread of the pixel shader andfor causing performance of EarlyZ to be skipped for all pixels in thesecond block.

Example 29 includes the subject matter of Examples 26-28, wherein saidcausing EarlyZ to be performed for all pixels in the first blockcomprises enabling EarlyZ for the first block.

Example 30 includes the subject matter of Examples 26-29, wherein saidcausing performance of EarlyZ to be skipped for all pixels in the secondblock comprises disabling EarlyZ for the second block.

Example 31 includes the subject matter of Examples 26-30, wherein saidmeans for launching further comprises: a means for generating a firststream of pixel updates that incorporates pixel shading characteristicsand for causing LateZ to be skipped for the first block; and a means forgenerating a second stream of pixel updates that incorporates pixelshading characteristics and for computing a depth value for all pixelsin the second block and causing LateZ to be performed for all pixels inthe second block.

Example 32 includes the subject matter of Examples 26-31, wherein saidmeans for causing LateZ to be skipped for the first block comprises ameans for outputting the first block to a stage subsequent to a LateZunit of the conservative rasterizer pipeline based on the second set ofinner coverage data.

Example 33 includes the subject matter of Examples 26-32, wherein saidmeans for causing LateZ to be performed for all pixels in the secondblock comprises a means for outputting the second block to a LateZ unitof the conservative rasterizer pipeline based on the second set of innercoverage data.

Some embodiments pertain to Example 34 that includes one or morenon-transitory computer-readable storage mediums having stored thereonexecutable computer program instructions that, when executed by one ormore processors, cause the one or more processors to perform operationsincluding: receiving a primitive to be rasterized; creating based on aplurality of vertices of the primitive, a pixel location stream and afirst set of inner coverage data for each pixel within the pixellocation stream, wherein first set of the inner coverage data isindicative of whether the corresponding pixel is fully covered by theprimitive or partially covered by the primitive; grouping based on thefirst set of inner coverage data pixels of the pixel location streaminto a first group and a second group, wherein the first group includesthose of the pixels that are fully covered by the primitive and thesecond group includes those pixels that are partially covered by theprimitive; and launching separate pixel shader processes for blocks ofpixels of the first group and blocks of pixels of the second group.

Example 35 includes the subject matter of Example 34, wherein theinstructions further cause the one or more processors to create a secondset of inner coverage data indicating at a pixel-block level (i) allpixels in the first block are fully covered by the primitive and (ii)all pixels in the second block are partially covered by the primitive.

Example 36 includes the subject matter of Examples 34-35 wherein saidlaunching separate pixel shader threads comprises: for a first block ofpixels of the first group, launching, by the conservative rasterizer, afirst thread of a pixel shader of the conservative rasterizer pipeline,including causing EarlyZ to be performed for all pixels in the firstblock; and for a second block of pixels of the second group, launching,by the conservative rasterizer, a second thread of the pixel shader andcausing performance of EarlyZ to be skipped for all pixels in the secondblock.

Example 37 includes the subject matter of Examples 34-36, wherein saidcausing EarlyZ to be performed for all pixels in the first blockcomprises enabling EarlyZ for the first block.

Example 38 includes the subject matter of Examples 34-37, wherein saidcausing performance of EarlyZ to be skipped for all pixels in the secondblock comprises disabling EarlyZ for the second block.

Example 39 includes the subject matter of Examples 34-38, wherein saidlaunching separate pixel shader threads further comprises: generating afirst stream of pixel updates that incorporates pixel shadingcharacteristics, including causing LateZ to be skipped for the firstblock; and generating a second stream of pixel updates that incorporatespixel shading characteristics, including computing a depth value for allpixels in the second block and causing LateZ to be performed for allpixels in the second block.

Example 40 includes the subject matter of Examples 34-39, wherein saidcausing LateZ to be skipped for the first block comprises outputting thefirst block to a stage subsequent to a LateZ unit based on the secondset of inner coverage data.

Example 41 includes the subject matter of Examples 34-40, wherein saidcausing LateZ to be performed for all pixels in the second blockcomprises outputting the second block to a LateZ unit based on thesecond set of inner coverage data.

Some embodiments pertain to Example 42 that includes a systemcomprising: a means for receiving a primitive to be rasterized; a meansfor creating based on a plurality of vertices of the primitive, a pixellocation stream and a first set of inner coverage data for each pixelwithin the pixel location stream, wherein first set of the innercoverage data is indicative of whether the corresponding pixel is fullycovered by the primitive or partially covered by the primitive; a meansfor grouping based on the first set of inner coverage data pixels of thepixel location stream into a first group and a second group, wherein thefirst group includes those of the pixels that are fully covered by theprimitive and the second group includes those pixels that are partiallycovered by the primitive; and a means for launching separate pixelshader processes for blocks of pixels of the first group and blocks ofpixels of the second group.

Example 43 includes the subject matter of Example 42, further comprisinga means for creating a second set of inner coverage data indicating at apixel-block level (i) all pixels in the first block are fully covered bythe primitive and (ii) all pixels in the second block are partiallycovered by the primitive.

Example 44 includes the subject matter of Examples 42-43, wherein themeans for launching separate pixel shader threads comprises: a means forlaunching for a first block of pixels of the first group a first pixelshader process and for causing EarlyZ to be performed for all pixels inthe first block; and a means for launching for a second block of pixelsof the second group a second pixel shader process and for causingperformance of EarlyZ to be skipped for all pixels in the second block.

Example 45 includes the subject matter of Examples 42-44, wherein saidcausing EarlyZ to be performed for all pixels in the first blockcomprises enabling EarlyZ for the first block.

Example 46 includes the subject matter of Examples 42-45, wherein saidcausing performance of EarlyZ to be skipped for all pixels in the secondblock comprises disabling EarlyZ for the second block.

Example 47 includes the subject matter of Examples 42-46, wherein saidmeans for launching separate pixel shader processes further comprises: ameans for generating a first stream of pixel updates that incorporatespixel shading characteristics and for causing LateZ to be skipped forthe first block; and a means for generating a second stream of pixelupdates that incorporates pixel shading characteristics, for computing adepth value for all pixels in the second block and for causing LateZ tobe performed for all pixels in the second block.

Example 48 includes the subject matter of Examples 42-47, wherein saidcausing LateZ to be skipped for the first block comprises outputting thefirst block to a stage subsequent to a LateZ unit of the conservativerasterizer pipeline based on the second set of inner coverage data.

Example 49 includes the subject matter of Examples 42-48, wherein saidcausing LateZ to be performed for all pixels in the second blockcomprises outputting the second block to a LateZ unit of theconservative rasterizer pipeline based on the second set of innercoverage data.

Some embodiments pertain to Example 50 that includes a computer systemthat includes a central processing unit and a GPU of any of Examples1-4.

Some embodiments pertain to Example 51 that includes a computer systemthat includes a central processing unit and a GPU of any of Examples10-12.

Some embodiments pertain to Example 52 that includes an apparatus thatimplements or performs a method of any of Examples 5-9.

Some embodiments pertain to Example 53 that includes an apparatus thatimplements or performs a method of any of Examples 13-20.

Example 54 includes at least one machine-readable medium comprising aplurality of instructions, when executed on a computing device, toimplement or perform a method or realize an apparatus as described inany preceding Example.

Example 55 includes an apparatus comprising means for performing amethod as claimed in any of Examples 5-9.

Example 56 includes an apparatus comprising means for performing amethod as claimed in any of Examples 13-20.

The drawings and the forgoing description give examples of embodiments.Those skilled in the art will appreciate that one or more of thedescribed elements may well be combined into a single functionalelement. Alternatively, certain elements may be split into multiplefunctional elements. Elements from one embodiment may be added toanother embodiment. For example, orders of processes described hereinmay be changed and are not limited to the manner described herein.Moreover, the actions of any flow diagram need not be implemented in theorder shown; nor do all of the acts necessarily need to be performed.Also, those acts that are not dependent on other acts may be performedin parallel with the other acts. The scope of embodiments is by no meanslimited by these specific examples. Numerous variations, whetherexplicitly given in the specification or not, such as differences instructure, dimension, and use of material, are possible. The scope ofembodiments is at least as broad as given by the following claims.

What is claimed is:
 1. A graphics processing unit (GPU) supportingEarlyZ for conservative rasterization, the GPU comprising: aconservative rasterizer operable to: process a primitive stream andgenerate (i) a pixel location stream based on vertices of a primitivefrom the primitive stream and (ii) inner coverage data for each pixelwithin the pixel location stream, wherein the inner coverage dataindicates for a given pixel within the pixel location stream whether thegiven pixel is fully covered by a primitive with which it is associatedor partially covered by the primitive; and launch pixel shaderprocessing for blocks of pixels of the pixel location stream, includingcausing early depth testing to be performed for those pixels of theblocks of pixels that are fully covered by the primitive and causingearly depth testing not to be performed for those pixels of the blocksof pixels that are partially covered by the primitive; and an EarlyZunit operable to perform the early depth testing to discard occludedpixels from the pixel location stream prior to pixel shading.
 2. The GPUof claim 1, further comprising: a plurality of pixel shaders operable toperform the pixel shader processing to generate pixel updates byconditionally processing the pixel location stream and incorporatingpixel shading characteristics into the pixel updates, including forthose pixels of the pixel location stream that are partially covered bythe primitive computing a depth value for the pixels and causing latedepth testing to be performed for the pixels; and a LateZ unit operableto perform the late depth testing to discard occluded pixels from thepixel updates.
 3. The GPU of claim 2, wherein the conservativerasterizer causes early depth testing to be performed by enabling theEarlyZ unit for those pixels of the block of pixels that are fullycovered by the primitive.
 4. The GPU of claim 2, wherein theconservative rasterizer causes early depth testing not to be performedby disabling the EarlyZ unit for those pixels of the block of pixelsthat are partially covered by the primitive.
 5. The GPU of claim 2,wherein the EarlyZ unit is operable to use the inner coverage data tomask out the early depth testing for partially covered pixels.
 6. Amethod for processing pixels by a conservative rasterization pipeline,the method comprising: receiving, by a conservative rasterizer of aconservative rasterizer pipeline of a graphics processing unit, aprimitive to be rasterized; creating, by the conservative rasterizer,based on a plurality of vertices of the primitive, a pixel locationstream and inner coverage data for each pixel within the pixel locationstream, wherein the inner coverage data is indicative of whether thecorresponding pixel is fully covered by the primitive or partiallycovered by the primitive; for each block of pixels of the pixel locationstream, launching, by the conservative rasterizer, a thread of a pixelshader of the conservative rasterizer pipeline, including causing EarlyZto be performed for those pixels of the block of pixels that are fullycovered by the primitive and causing EarlyZ not to be performed forthose pixels of the block of pixels that are partially covered by theprimitive; and generating, by the pixel shader, a stream of pixelupdates by conditionally processing the pixel location stream toincorporate pixel shading characteristics, including for those pixels ofthe pixel location stream that are partially covered by the primitivecomputing a depth value for the pixels and causing LateZ to be performedfor the pixels.
 7. The method of claim 6, wherein said causing EarlyZ tobe performed comprises enabling EarlyZ for those pixels of the block ofpixels that are fully covered by the primitive.
 8. The method of claim6, wherein said causing EarlyZ not to be performed comprises bypassingEarlyZ for those pixels of the block of pixels that are partiallycovered by the primitive.
 9. The method of claim 6, wherein said causingEarlyZ not to be performed comprises disabling EarlyZ for those pixelsof the block of pixels that are partially covered by the primitive. 10.The method of claim 6, wherein said causing EarlyZ not to be performedcomprises causing an EarlyZ unit to conditionally process pixels of thepixel location stream based on the inner coverage data including passingthrough unchanged those pixels of the block of pixels that are partiallycovered by the primitive.
 11. A conservative rasterization pipeline of agraphics processing unit (GPU), the conservative rasterization pipelinecomprising: a conservative rasterizer operable to: generate (i) a pixellocation stream based on vertices of a primitive and (ii) inner coveragedata for each pixel within the pixel location stream; and cause earlydepth testing to be performed for those pixels within the pixel locationstream that are fully covered by the primitive (“fully covered pixels”)and early depth testing not to be performed for those pixels within thepixel location stream that are partially covered by the primitive(“partially covered pixels”), wherein the inner coverage data indicatesfor a given pixel within the pixel location stream whether the givenpixel is fully or partially covered by the primitive; and an EarlyZ unitoperable to perform the early depth testing based on the inner coveragedata to discard occluded pixels from the pixel location stream prior topixel shading; a pixel shader operable to generate pixel updates byconditionally processing the pixel location stream and incorporatingpixel shading characteristics into the pixel updates, including depthvalues for the partially covered pixels; and a LateZ unit operable toperform late depth testing based on the inner coverage data and thedepth values to discard occluded pixels from the pixel updates.
 12. Theconservative rasterization pipeline of claim 11, wherein theconservative rasterizer causes the early depth testing to be performedby enabling the EarlyZ unit for the fully covered pixels.
 13. Theconservative rasterization pipeline of claim 12, wherein theconservative rasterizer causes the early depth testing not to beperformed by disabling the EarlyZ unit for the partially covered pixels.14. The conservative rasterization pipeline of claim 11, wherein theEarlyZ unit is operable to use the inner coverage data to mask outresults of the early depth testing for the partially covered pixels. 15.A method for processing pixels by a conservative rasterization pipelineof a graphics processing unit (GPU), the method comprising: creatingbased on a plurality of vertices of a primitive, a pixel location streamand inner coverage data for each pixel within the pixel location stream,wherein the inner coverage data is indicative of whether thecorresponding pixel is fully covered by the primitive or partiallycovered by the primitive; for each block of pixels of the pixel locationstream, causing EarlyZ to be performed prior to pixel shading for thosepixels of the block of pixels that are fully covered by the primitiveand causing EarlyZ not to be performed prior to the pixel shading forthose pixels of the block of pixels that are partially covered by theprimitive; generating, by a pixel shader of the conservativerasterization pipeline, a stream of pixel updates by conditionallyprocessing the pixel location stream to incorporate pixel shadingcharacteristics, including for those pixels of the pixel location streamthat are partially covered by the primitive computing depth values forthe pixels; discarding occluded pixels from the pixel updates byperforming late depth testing on the pixels based on the inner coveragedata and the depth values.
 16. The method of claim 15, wherein saidcausing EarlyZ to be performed comprises enabling EarlyZ for thosepixels of the block of pixels that are fully covered by the primitive.17. The method of claim 15, wherein said causing EarlyZ not to beperformed comprises bypassing EarlyZ for those pixels of the block ofpixels that are partially covered by the primitive.
 18. The method ofclaim 15, wherein said causing EarlyZ not to be performed comprisesdisabling EarlyZ for those pixels of the block of pixels that arepartially covered by the primitive.
 19. The method of claim 15, whereinsaid causing EarlyZ not to be performed comprises causing an EarlyZ unitof the conservative rasterization pipeline to conditionally processpixels of the pixel location stream based on the inner coverage dataincluding passing through unchanged those pixels of the block of pixelsthat are partially covered by the primitive.